SDI Audio Intel FPGA IP User Guide

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ID 683333
Date 6/21/2022
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Document Table of Contents
Document Table of Contents x
1. SDI Audio Intel FPGA IP Overview 2. SDI Audio Intel FPGA IP Getting Started 3. SDI Audio Intel FPGA IP Functional Description 4. SDI Audio Intel FPGA IP Parameters 5. SDI Audio Intel FPGA IP Interface Signals 6. SDI Audio Intel FPGA IP Registers 7. SDI Audio Intel FPGA IP User Guide Archives 8. Document Revision History for the SDI Audio Intel FPGA IP User Guide
1. SDI Audio Intel FPGA IP Overview x
1.1. Release Information
2. SDI Audio Intel FPGA IP Getting Started x
2.1. Instantiating the SDI Audio Intel FPGA IP Simulating the Testbench
3. SDI Audio Intel FPGA IP Functional Description x
3.1. SDI Audio Embed IP Core 3.2. SDI Audio Extract IP Core 3.3. SDI Clocked Audio Input IP Core 3.4. SDI Clocked Audio Output IP Core 3.5. AES Format 3.6. Avalon-ST Audio Interface
4. SDI Audio Intel FPGA IP Parameters x
4.1. SDI Audio Embed Parameters 4.2. SDI Audio Extract Parameters 4.3. SDI Audio Clocked Audio Input Parameters 4.4. SDI Audio Clocked Audio Output Parameters
5. SDI Audio Intel FPGA IP Interface Signals x
5.1. SDI Audio Embed Signals 5.2. SDI Audio Extract Signals 5.3. SDI Audio Clocked Input Signals 5.4. SDI Audio Clocked Output Signals 5.5. SDI Audio IP Register Interface Signals
6. SDI Audio Intel FPGA IP Registers x
6.1. SDI Audio Embed Registers 6.2. SDI Audio Extract Registers 6.3. SDI Clocked Audio Input Registers 6.4. SDI Clocked Audio Output Registers
1. SDI Audio Intel FPGA IP Overview
2. SDI Audio Intel FPGA IP Getting Started
3. SDI Audio Intel FPGA IP Functional Description
4. SDI Audio Intel FPGA IP Parameters
5. SDI Audio Intel FPGA IP Interface Signals
6. SDI Audio Intel FPGA IP Registers
7. SDI Audio Intel FPGA IP User Guide Archives
8. Document Revision History for the SDI Audio Intel FPGA IP User Guide

5.3. SDI Audio Clocked Input Signals

The following tables list the signals for the SDI Audio Clocked Input IP cores.

This table lists the input and output signals.

Table 19.  SDI Audio Clocked Input Input and Output Signals

Signal

Width

Direction

Description

aes_clk

[0:0]

Input

Audio input clock.
aes_de

[0:0]

Input

Audio data enable.
aes_ws

[0:0]

Input

Audio word select.
aes_data

[0:0]

Input

Audio data input in internal AES format.

This table lists the Avalon-ST audio signals when you instantiate the SDI Audio Clocked Input IP core in Platform Designer (Standard).

Table 20.  SDI Audio Clocked Input Avalon-ST Audio Signals

Signal

Width

Direction

Description

aud_clk

[0:0]

Input

Clocked audio clock. All the audio input signals are synchronous to this clock.
aud_ready

[0:0]

Input

Avalon-ST ready signal. Assert this signal when the device is able to receive data.
aud_valid

[0:0]

Output

Avalon-ST valid signal. The core asserts this signal when it produces data.

aud_sop

[0:0]

Output

Avalon-ST start of packet signal. The core asserts this signal when it is starting a new frame.
aud_eop

[0:0]

Output

Avalon-ST end of packet signal. The core asserts this signal when it is ending a frame.
aud_data

[23:0]

Output

Avalon-ST data bus. The core asserts this signal to transfer data.

This table lists the direct control interface signals. The direct control interface is internal to the audio extract component.

Table 21.  SDI Audio Clocked Input Direct Control Interface Signals

Signal

Width

Direction

Description

channel0

[7:0]

Input

Indicates the channel number of audio channel 1.
channel1

[7:0]

Input

Indicates the channel number of audio channel 2.
fifo_status

[7:0]

Input

Drive bit 7 high to reset the clocked audio input FIFO buffer.
fifo_reset [0:0] Output Assert this signal when the clocked audio input FIFO buffer overflows.
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