SDI Audio Intel FPGA IP User Guide

Download PDF
ID 683333
Date 6/21/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. SDI Audio Intel FPGA IP Overview 2. SDI Audio Intel FPGA IP Getting Started 3. SDI Audio Intel FPGA IP Functional Description 4. SDI Audio Intel FPGA IP Parameters 5. SDI Audio Intel FPGA IP Interface Signals 6. SDI Audio Intel FPGA IP Registers 7. SDI Audio Intel FPGA IP User Guide Archives 8. Document Revision History for the SDI Audio Intel FPGA IP User Guide
1. SDI Audio Intel FPGA IP Overview x
1.1. Release Information
2. SDI Audio Intel FPGA IP Getting Started x
2.1. Instantiating the SDI Audio Intel FPGA IP Simulating the Testbench
3. SDI Audio Intel FPGA IP Functional Description x
3.1. SDI Audio Embed IP Core 3.2. SDI Audio Extract IP Core 3.3. SDI Clocked Audio Input IP Core 3.4. SDI Clocked Audio Output IP Core 3.5. AES Format 3.6. Avalon-ST Audio Interface
4. SDI Audio Intel FPGA IP Parameters x
4.1. SDI Audio Embed Parameters 4.2. SDI Audio Extract Parameters 4.3. SDI Audio Clocked Audio Input Parameters 4.4. SDI Audio Clocked Audio Output Parameters
5. SDI Audio Intel FPGA IP Interface Signals x
5.1. SDI Audio Embed Signals 5.2. SDI Audio Extract Signals 5.3. SDI Audio Clocked Input Signals 5.4. SDI Audio Clocked Output Signals 5.5. SDI Audio IP Register Interface Signals
6. SDI Audio Intel FPGA IP Registers x
6.1. SDI Audio Embed Registers 6.2. SDI Audio Extract Registers 6.3. SDI Clocked Audio Input Registers 6.4. SDI Clocked Audio Output Registers
1. SDI Audio Intel FPGA IP Overview
2. SDI Audio Intel FPGA IP Getting Started
3. SDI Audio Intel FPGA IP Functional Description
4. SDI Audio Intel FPGA IP Parameters
5. SDI Audio Intel FPGA IP Interface Signals
6. SDI Audio Intel FPGA IP Registers
7. SDI Audio Intel FPGA IP User Guide Archives
8. Document Revision History for the SDI Audio Intel FPGA IP User Guide

8. Document Revision History for the SDI Audio Intel FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.06.21 22.2 19.1.2 Added Intel® Stratix® 10 device support.
2021.12.15 21.4 19.1.1 Added Intel® Agilex™ device support.
2020.10.05 19.2 19.1.0 Updated the ordering code. The new ordering code is IP-SDI-II.
2019.07.24 19.2 19.1.0
  • Updated introductory description of SDI Audio Intel® FPGA IP cores in SDI Audio Intel® FPGA IP Overview chapter.
  • Added notes on availability of SDI Audio Intel® FPGA IP cores in the Intel® Quartus® Prime Pro Edition software and Intel® Quartus® Prime Standard Edition software in the SDI Audio Intel® FPGA IP Overview chapter.
  • Added Release Information section in the SDI Audio Intel® FPGA IP Overview chapter.
  • Moved release information and device family support information into Release Information section.
  • Renamed item Version to IP Version and added item Intel Quartus Prime Version in Table: SDI Audio Intel® FPGA IP Cores Current Release Information.
  • Added support information for Intel® Arria® 10 GX, Intel® Arria® 10 GT, and Intel® Arria® 10 SX device families in Table: SDI Audio Intel® FPGA IP Cores Current Release Information.
  • Removed support information for Arria® II GX, Arria V, Cyclone® IV GX, Cyclone V, Stratix® IV GX, and Stratix V FPGA device families in Table: SDI Audio Intel® FPGA IP Cores Current Release Information.
  • Removed references to "Standard" associated with Platform Designer, added note on instantiating IP through IP Catalog using the IP parameter editor, and removed notes on instantiating IP in RTL in the Instantiating the SDI Audio Intel® FPGA IP section.
  • Added Table: SDI Audio IP Cores to Generate in Simulating the Testbench section.
  • Updated procedure in Simulating the Testbench section.
  • Updated description for parameter Async Audio Interface to indicate that this mode supports an audio clock equal to or higher than 64 × sample rate, added description that the parameters Frequency of fix_clk and Cleanly remove existing audio are not supported in the Intel® Quartus® Prime Pro Edition software, and added parameter Parallel Audio Interface in Table: SDI Audio Embed Parameters.
  • Added parameters Async Audio Interface and Parallel Audio Interface in Table: SDI Audio Extract Parameters.
  • Added parallel mode width and description for signal aud_data in Table: SDI Audio Embed Audio Input Signals and Table: SDI Audio Extract Audio Input and Output Signals.
  • Added description to signals strip_control and strip_status that the Intel® Quartus® Prime Pro Edition software SDI Audio Intel® FPGA IP does not support strip control and strip status in Table: SDI Audio Embed Direct Control Interface Signals.
  • Added note for the strip control register and strip status register that the Intel® Quartus® Prime Pro Edition software SDI Audio Intel® FPGA IP does not support strip control and strip status in Table: SDI Audio Embed Register Map.
  • Removed SDI Audio Intel® FPGA IP Design Example chapter.
    Note: Intel provides a design example with the SDI Audio Embed and Extract IP cores in the Intel® Quartus® Prime Standard Edition software only. Refer to the user guide for the previous IP core version (18.0) for information.
  • Added explanation on the new IP versioning scheme in the SDI Audio Intel® FPGA IP User Guide Archives chapter.
2018.05.16 18.0 18.0
  • Rebranded as Intel.
  • Edited the vid_std settings for SDI Audio Extract IP core. The correct settings should be 10b for 3G-SDI Level B and 11b for 3G-SDI Level A.
  • Removed Audio group presence register (bit 3:0). The register is no longer supported in the current IP code.
Date Version Changes
May 2016 2016.05.30
  • Added a new signal for the SDI Audio Extract IP core: aud_z[0:0]. This signal indicates the Z preamble.
  • Added the default values that replace the channel status data when you set the CS mode select register to 01b.
  • Added link to an archived version of the SDI Audio IP Cores User Guide.
  • Changed instances of Quartus II to Quartus Prime.

June 2014

2014.06.30

  • Created a separate user guide for the SDI Audio IP cores.
  • Removed the SDI Audio IP section from the SDI IP Core User Guide.
  • Added new registers for the SDI Audio Embed IP core: SD EDP Control, Strip Control, and Strip Status.
  • Added new signals for the SDI Audio Embed IP core: extended_control, strip_control, and strip_control.
  • Added a new register for the SDI Audio Extract IP core: SD EDP Presence.
  • Added a new signal for the SDI Audio Extract IP core: sd_edp_presence.
Level Two Title