SDI Audio Intel FPGA IP User Guide

ID 683333
Date 12/15/2021
Public

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6.4. SDI Clocked Audio Output Registers

The following tables list the registers for the SDI Clocked Audio Output IP core.

Table 31.  SDI Clocked Audio Output Register Map

Bytes Offset

Name

00h

Channel 0 Register

01h

Channel 1 Register

02h

FIFO Status Register

03h

FIFO Reset Register

Table 32.  SDI Clocked Audio Output Registers

Bit

Name

Access

Description

Channel 0 Register

7:0

Channel 0

RW

The user-defined channel number of audio channel 0.

Channel 1 Register

7:0

Channel status RAM select

RW

The user-defined channel number of audio channel 1.

FIFO Status Register

7:0

Active channel

RO

This sticky bit reports the overflow of the clocked audio output FIFO.

FIFO Reset Register

6:0

Unused

WO

Reserved for future use.

7 FIFO reset WO Resets the clocked audio FIFO.