SDI Audio Intel FPGA IP User Guide

ID 683333
Date 12/15/2021
Public

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5.3. SDI Audio Clocked Input Signals

The following tables list the signals for the SDI Audio Clocked Input IP cores.

This table lists the input and output signals.

Table 19.  SDI Audio Clocked Input Input and Output Signals

Signal

Width

Direction

Description

aes_clk

[0:0]

Input

Audio input clock.
aes_de

[0:0]

Input

Audio data enable.
aes_ws

[0:0]

Input

Audio word select.
aes_data

[0:0]

Input

Audio data input in internal AES format.

This table lists the Avalon-ST audio signals when you instantiate the SDI Audio Clocked Input IP core in Platform Designer (Standard).

Table 20.  SDI Audio Clocked Input Avalon-ST Audio Signals

Signal

Width

Direction

Description

aud_clk

[0:0]

Input

Clocked audio clock. All the audio input signals are synchronous to this clock.
aud_ready

[0:0]

Input

Avalon-ST ready signal. Assert this signal when the device is able to receive data.
aud_valid

[0:0]

Output

Avalon-ST valid signal. The core asserts this signal when it produces data.

aud_sop

[0:0]

Output

Avalon-ST start of packet signal. The core asserts this signal when it is starting a new frame.
aud_eop

[0:0]

Output

Avalon-ST end of packet signal. The core asserts this signal when it is ending a frame.
aud_data

[23:0]

Output

Avalon-ST data bus. The core asserts this signal to transfer data.

This table lists the direct control interface signals. The direct control interface is internal to the audio extract component.

Table 21.  SDI Audio Clocked Input Direct Control Interface Signals

Signal

Width

Direction

Description

channel0

[7:0]

Input

Indicates the channel number of audio channel 1.
channel1

[7:0]

Input

Indicates the channel number of audio channel 2.
fifo_status

[7:0]

Input

Drive bit 7 high to reset the clocked audio input FIFO buffer.
fifo_reset [0:0] Output Assert this signal when the clocked audio input FIFO buffer overflows.