SDI Audio Intel FPGA IP User Guide

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ID 683333
Date 12/15/2021
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Document Table of Contents
Document Table of Contents x
1. SDI Audio Intel FPGA IP Overview 2. SDI Audio Intel FPGA IP Getting Started 3. SDI Audio Intel FPGA IP Functional Description 4. SDI Audio Intel FPGA IP Parameters 5. SDI Audio Intel FPGA IP Interface Signals 6. SDI Audio Intel FPGA IP Registers 7. SDI Audio Intel FPGA IP User Guide Archives 8. Document Revision History for the SDI Audio Intel FPGA IP User Guide
1. SDI Audio Intel FPGA IP Overview x
1.1. Release Information
2. SDI Audio Intel FPGA IP Getting Started x
2.1. Instantiating the SDI Audio Intel FPGA IP Simulating the Testbench
3. SDI Audio Intel FPGA IP Functional Description x
3.1. SDI Audio Embed IP Core 3.2. SDI Audio Extract IP Core 3.3. SDI Clocked Audio Input IP Core 3.4. SDI Clocked Audio Output IP Core 3.5. AES Format 3.6. Avalon-ST Audio Interface
4. SDI Audio Intel FPGA IP Parameters x
4.1. SDI Audio Embed Parameters 4.2. SDI Audio Extract Parameters 4.3. SDI Audio Clocked Audio Input Parameters 4.4. SDI Audio Clocked Audio Output Parameters
5. SDI Audio Intel FPGA IP Interface Signals x
5.1. SDI Audio Embed Signals 5.2. SDI Audio Extract Signals 5.3. SDI Audio Clocked Input Signals 5.4. SDI Audio Clocked Output Signals 5.5. SDI Audio IP Register Interface Signals
6. SDI Audio Intel FPGA IP Registers x
6.1. SDI Audio Embed Registers 6.2. SDI Audio Extract Registers 6.3. SDI Clocked Audio Input Registers 6.4. SDI Clocked Audio Output Registers
1. SDI Audio Intel FPGA IP Overview
2. SDI Audio Intel FPGA IP Getting Started
3. SDI Audio Intel FPGA IP Functional Description
4. SDI Audio Intel FPGA IP Parameters
5. SDI Audio Intel FPGA IP Interface Signals
6. SDI Audio Intel FPGA IP Registers
7. SDI Audio Intel FPGA IP User Guide Archives
8. Document Revision History for the SDI Audio Intel FPGA IP User Guide

5.1. SDI Audio Embed Signals

The following tables list the signals for the SDI Audio Embed IP cores.

This table lists the general input and output signals.

Table 8.  SDI Audio Embed General Input and Output Signals

Signal

Width

Direction

Description

reset

[0:0]

Input

This signal resets the system.

fix_clk

[0:0]

Input

This signal provides the frequency reference used when detecting the difference between video standards using 1 and 1/1.001 clock rates. If its frequency is 0, the signal only detects either one of the clock rates.

The core limits the possible frequencies for this signal to 24.576 MHz, 25 MHz, 50 MHz, 100 MHz, and 200 MHz. Set the required frequency using the Frequency of fix_clk parameter.

vid_std_rate

[0:0]

Input

If you set the Frequency of fix_clk parameter to 0, you must drive this signal high to detect a video frame rate of 1/1.001 and low to detect a video frame rate of 1. For other settings of the Frequency of fix_clk parameter, the core automatically detects these frame rates and drives this signal low.

vid_clk48

[0:0]

Output

The 48 kHz output clock that is synchronous to the video. This clock signal is only available when you turn on the Frequency Sine Wave Generator or Include Clock parameter.

This table lists the video input and output signals.

Table 9.  SDI Audio Embed Video Input and Output Signals

Signal

Width

Direction

Description

vid_clk

[0:0]

Input

The video clock that is typically 27 MHz for SD-SDI, 74.25 MHz or 74.17 MHz for HD-SDI, or 148.5 MHz or 148.35 MHz for 3G-SDI standards. You can use higher clock rates with the vid_datavalid signal.

Set exclusive clock group to aud_clk and vid_clk to prevent unstable or flickering image.

vid_std

[1:0]

Input

Indicates the received video standard. Applicable for 3G-SDI, dual standard, and triple standard modes only.

Set this signal to indicate the following formats:

  • [00] for10-bit SD-SDI
  • [01] for 20-bit HD-SDI
  • [10] for 3G-SDI Level B
  • [11] for 3G-SDI Level A
vid_datavalid

[0:0]

Input

Assert this signal when the video data is valid.

vid_data

[19:0]

Input

Receiver protocol reset signal. This signal must be driven by the rx_rst_proto_out reset signal from the transceiver block.

This signal carries luma and chroma information.

SD-SDI:

  • [19:10] Unused
  • [9:0] Cb,Y, Cr, Y multiplex

HD-SDI and 3G-SDI Level A:

  • [19:10] Y
  • [9:0] C

3G-SDI Level B:

  • [19:10] Cb,Y, Cr, Y multiplex (link A)
  • [9:0] Cb,Y, Cr, Y multiplex (link B)
vid_out_datavalid

[0:0]

Output

The core drives this signal high during valid output video clock cycles.

vid_out_trs

[0:0]

Output

The core drives this signal high during the first 3FF clock cycle of a video timing reference signal; the first two 3FF cycles for 3G-SDI Level B. This signal provides easy connection to the SDI IP cores.

vid_out_ln

[10:0]

Output

The video line signal that provides for easy connection to the SDI IP cores. To observe the correct video out line number, allow two-frame duration for the audio embed IP to correctly embed and show the line number.

vid_out_data

[19:0]

Output

The video output signal.

This table lists the audio input signals.

Table 10.  SDI Audio Embed Audio Input Signals N is the number of audio group.

Signal

Width

Direction

Description

aud_clk

[2N–1:0]

Input

Set this clock to 3.072 MHz that is synchronous to the extracted audio. In asynchronous mode, set this to any frequency above 3.072 MHz. Intel recommends that you set this clock to 50 MHz.

For SD-SDI inputs, this mode of operation limits the core to embedding audio that is synchronous to the video. For HD-SDI inputs, this clock must either be generated from the optional 48 Hz output or the audio must be synchronous to the video.

Set exclusive clock group to aud_clk and vid_clk to prevent unstable or flickering image.

aud_de

[2N–1:0]

Input

Assert this data enable signal to indicate valid information on the aud_ws and aud_data signals.

In synchronous mode, the core ignores this signal.

aud_ws

[2N–1:0]

Input

Assert this word select signal to provide framing for deserialization and to indicate left or right sample of channel pair.

aud_data

[2N–1:0]

Input

Internal AES data signal from the AES input module.

In parallel mode, each audio pair is 32 bits wide. Total width in parallel mode is [(32*2N)–1:0].

[(32*2N)–1:0]

Input

This table lists the Avalon-ST audio signals when you instantiate the SDI Audio Embed IP core in Platform Designer (Standard).

Table 11.  SDI Audio Embed Avalon-ST Audio Signals n is the number of audio channels, the value starts from 0 to n-1.

Signal

Width

Direction

Description

aud(n)_clk

[0:0]

Input

Clocked audio clock. All the audio input signals are synchronous to this clock.
aud(n)_ready

[0:0]

Output

Avalon-ST ready signal. Assert this signal when the device is able to receive data.
aud(n)_valid

[0:0]

Input

Avalon-ST valid signal. The core asserts this signal when it receives data.

aud(n)_sop

[0:0]

Input

Avalon-ST start of packet signal. The core asserts this signal when it is starting a new frame.
aud(n)_eop

[0:0]

Input

Avalon-ST end of packet signal. The core asserts this signal when it is ending a frame.
aud(n)_channel

[7:0]

Input

Avalon-ST select signal. Use this signal to select a specific channel.
aud(n)_data

[23:0]

Input

Avalon-ST data bus. This bus transfers data.

This table lists the register interface signals. The register interface is a standard 8-bit wide Avalon-MM slave.
Table 12.  SDI Audio Embed Register Interface Signals

Signal

Width

Direction

Description

reg_clk

[0:0]

Input

Clock for the Avalon-MM register interface.
reg_reset

[0:0]

Input

Reset for the Avalon-MM register interface.
reg_base_addr

[5:0]

Input

Reset for the Avalon-MM register interface.

reg_burst_count

[5:0]

Input

Transfer size in bytes.
reg_waitrequest

[0:0]

Output

Wait request.
reg_write

[7:0]

Input

Write request.
reg_writedata

[0:0]

Input

Data to be written to target.
reg_read [0:0] Input Read request.
reg_readdatavalid [0:0] Output Requested read data valid after read latency.
reg_readdata [7:0] Output Data read from target.

This table lists the direct control interface signals. These signals are exposed as ports if you turn off the Include Avalon-MM Control Interface parameter.
Table 13.  SDI Audio Embed Direct Control Interface Signals

Signal

Width

Direction

Description

reg_clk

[0:0]

Input

Clock for the direct control interface.
audio_control

[7:0]

Input

Assert this 8-bit signal to enable the audio channels. Each bit controls one audio channel.
extended_control

[7:0]

Input

This signal does the same function as the extended control register.
video_status

[7:0]

Output

This signal does the same function as the video status register.
sd_edp_control [7:0] Output This signal does the same function as the SD EDP control register.
audio_status

[7:0]

Output

This signal does the same function as the audio status register.
cs_control

[15:0]

Input

This signal does the same function as the channel status control register.
strip_control [7:0]

Input

This signal does the same function as the strip control register.

The Intel® Quartus® Prime Pro Edition software SDI Audio Intel® FPGA IP does not support strip control.

strip_status

[7:0]

Output

This signal does the same function as the strip status register.

The Intel® Quartus® Prime Pro Edition software SDI Audio Intel® FPGA IP does not support strip status.

sine_freq_ch1

[7:0]

Input

This signal does the same function as the sine channel 1 frequency register.
sine_freq_ch2 [7:0] Input This signal does the same function as the sine channel 2 frequency register.
sine_freq_ch3 [7:0] Input This signal does the same function as the sine channel 3 frequency register.
sine_freq_ch4 [7:0] Input This signal does the same function as the sine channel 4 frequency register.
csram_addr [5:0] Input Channel status RAM address.
csram_we [0:0] Input

Drive this signal high for a single cycle of reg_clk signal to load the value of the csram_data port into the channel status RAM at the address on the csram_addr port.

If each input audio pair gets separate channel status RAMs, this signal addresses the RAM selected by the extended_control port.

csram_data [7:0] Input Channel status data. This signal does the same function as the channel status RAM register in Table 4–9.
Related Information
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