SDI Audio Intel FPGA IP User Guide

ID 683333
Date 12/15/2021
Public

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5.5. SDI Audio IP Register Interface Signals

All SDI Audio IP cores use the same register interface signals.

The register interface is a standard 8-bit wide Avalon-MM slave.
Table 24.  SDI Audio IP Register Interface Signals

Signal

Width

Direction

Description

reg_clk

[0:0]

Input

Clock for the Avalon-MM register interface.
reg_reset

[0:0]

Input

Reset for the Avalon-MM register interface.
reg_base_addr

[5:0]

Input

Reset for the Avalon-MM register interface.

reg_burst_count

[5:0]

Input

Transfer size in bytes.
reg_waitrequest

[0:0]

Output

Wait request.
reg_write

[7:0]

Input

Write request.
reg_writedata

[0:0]

Input

Data to be written to target.
reg_read

[0:0]

Input

Read request.
reg_readdatavalid

[0:0]

Output

Requested read data valid after read latency.
reg_readdata

[7:0]

Output

Data read from target.