SDI Audio Intel FPGA IP User Guide

Download PDF
ID 683333
Date 12/15/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. SDI Audio Intel FPGA IP Overview 2. SDI Audio Intel FPGA IP Getting Started 3. SDI Audio Intel FPGA IP Functional Description 4. SDI Audio Intel FPGA IP Parameters 5. SDI Audio Intel FPGA IP Interface Signals 6. SDI Audio Intel FPGA IP Registers 7. SDI Audio Intel FPGA IP User Guide Archives 8. Document Revision History for the SDI Audio Intel FPGA IP User Guide
1. SDI Audio Intel FPGA IP Overview x
1.1. Release Information
2. SDI Audio Intel FPGA IP Getting Started x
2.1. Instantiating the SDI Audio Intel FPGA IP Simulating the Testbench
3. SDI Audio Intel FPGA IP Functional Description x
3.1. SDI Audio Embed IP Core 3.2. SDI Audio Extract IP Core 3.3. SDI Clocked Audio Input IP Core 3.4. SDI Clocked Audio Output IP Core 3.5. AES Format 3.6. Avalon-ST Audio Interface
4. SDI Audio Intel FPGA IP Parameters x
4.1. SDI Audio Embed Parameters 4.2. SDI Audio Extract Parameters 4.3. SDI Audio Clocked Audio Input Parameters 4.4. SDI Audio Clocked Audio Output Parameters
5. SDI Audio Intel FPGA IP Interface Signals x
5.1. SDI Audio Embed Signals 5.2. SDI Audio Extract Signals 5.3. SDI Audio Clocked Input Signals 5.4. SDI Audio Clocked Output Signals 5.5. SDI Audio IP Register Interface Signals
6. SDI Audio Intel FPGA IP Registers x
6.1. SDI Audio Embed Registers 6.2. SDI Audio Extract Registers 6.3. SDI Clocked Audio Input Registers 6.4. SDI Clocked Audio Output Registers
1. SDI Audio Intel FPGA IP Overview
2. SDI Audio Intel FPGA IP Getting Started
3. SDI Audio Intel FPGA IP Functional Description
4. SDI Audio Intel FPGA IP Parameters
5. SDI Audio Intel FPGA IP Interface Signals
6. SDI Audio Intel FPGA IP Registers
7. SDI Audio Intel FPGA IP User Guide Archives
8. Document Revision History for the SDI Audio Intel FPGA IP User Guide

4.1. SDI Audio Embed Parameters

The following table lists the parameters for the SDI Audio Embed IP core.

Table 4.   SDI Audio Embed Parameters

Parameter

Value

Description

Number of supported audio groups

1, 2, 3, 4

Specifies the maximum number of audio groups supported.

Each audio group consists of 4 audio channels (2 channel pairs). You must specify all the four channels to the same sample frequencies.

Async Audio Interface

On or Off

Turn on to enable the Asynchronous input.

This mode supports an audio clock equal to or higher than 64 × sample rate.

Parallel Audio Interface

On or Off

Turn on to send AES data in parallel mode with a 32-bit parallel interface.

Requires Async Audio Interface to be turned on.

Frequency of fix_clk

0, 24.576, 25, 50, 100, 200

Sets the expected frequency of the fix_clk input; used as frequency reference when detecting the difference between video rate of 1/1.000 or 1/1.001.

Setting this parameter to 0 drives fix_clk low.

The Intel® Quartus® Prime Pro Edition software does not support this parameter.

Include SD-SDI 24-bit support

On or Off

Enables the embedding of SD-SDI Extended Data Packets (EDP) for each audio group.
Cleanly remove existing audio

0,1, 2

Enables the removal of existing embedded audio data.

When set to 1, the system requires extra storage to delay the video and remove any existing audio from SD-SDI, HD-SDI, or 3G-SDI Level A standard.

When set to 2, the system includes extra storage to remove the existing audio from 3G-SDI Level B standard.

Select 0 to turn off this parameter.

The Intel® Quartus® Prime Pro Edition software does not support this parameter.

Channel status RAM

0,1, 2

Enables storage of the custom channel status data.

Select 1 to generate a single channel status RAM, or 2 to generate separate RAMs for each input audio pair.

Select 0 to turn off this parameter.

Frequency sine wave generator

On or Off

Turn on to enable a four-frequency sine wave generator.

You can use the four-frequency sine wave generator as a test source for the audio embedder.

Include clock

On or Off

Turn on to enable a 48-kHz pulse generator synchronous to the video clock. You can use the 48-kHz pulse generator to request data from a sample rate converter.

When you turn on the Frequency Sine Wave Generator parameter, the core automatically includes this pulse generator.

Include Avalon-ST interface

On or Off

Turn on to include the SDI Clocked Audio Output IP core.

When you turn on this parameter, the Avalon-ST interface signals appear at the top level. Otherwise, the audio input signals appear at the top level.

Include Avalon-MM control interface

On or Off

Turn on to include the Avalon-MM control interface.

When you turn on this parameter, the register interface signals appear at the top level. Otherwise, the direct control interface signals appear at the top level.

Related Information
Level Two Title