Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Tone Mapping Operator Intel® FPGA IP 43. Test Pattern Generator Intel® FPGA IP 44. Unsharp Mask Intel® FPGA IP 45. Video and Vision Monitor Intel FPGA IP 46. Video Frame Buffer Intel® FPGA IP 47. Video Frame Reader Intel FPGA IP 48. Video Frame Writer Intel FPGA IP 49. Video Streaming FIFO Intel® FPGA IP 50. Video Timing Generator Intel® FPGA IP 51. Vignette Correction Intel® FPGA IP 52. Warp Intel® FPGA IP 53. White Balance Correction Intel® FPGA IP 54. White Balance Statistics Intel® FPGA IP 55. Design Security 56. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 1D LUT Intel® FPGA IP x
8.1. About the 1D LUT IP 8.2. 1D LUT IP Parameters 8.3. 1D LUT IP Interfaces 8.4. 1D LUT IP Registers 8.5. 1D LUT IP Software API
8.1. About the 1D LUT IP x
8.1.1. 1D LUT IP Performance and Resources
9. 3D LUT Intel® FPGA IP x
9.1. About the 3D LUT Intel® FPGA IP 9.2. 3D LUT IP Parameters 9.3. 3D LUT IP Block Description 9.4. 3D LUT IP Registers 9.5. 3D LUT IP Software API
9.1. About the 3D LUT Intel® FPGA IP x
9.1.1. 3D LUT IP Features 9.1.2. 3D LUT IP Performance IP and Resource Information
9.3. 3D LUT IP Block Description x
9.3.1. 3D LUT IP Interfaces 9.3.2. 3D LUT IP Latency
10. Adaptive Noise Reduction Intel® FPGA IP x
10.1. About the Adaptive Noise Reduction IP 10.2. Adaptive Noise Reduction IP Parameters 10.3. Adaptive Noise Reduction IP Functional Description 10.4. Adaptive Noise Reduction IP Registers 10.5. Adaptive Noise Reduction IP Software API
10.1. About the Adaptive Noise Reduction IP x
10.1.1. Adaptive Noise Reduction IP Performance and Resources
10.3. Adaptive Noise Reduction IP Functional Description x
10.3.1. Adaptive Noise Reduction IP Interfaces
11. Advanced Test Pattern Generator Intel® FPGA IP x
11.1. About the Advanced Test Pattern Generator IP 11.2. Advanced Test Pattern Generator IP Parameters 11.3. Advanced Test Pattern Generator IP Functional Description 11.4. Advanced Test Pattern Generator IP Registers 11.5. Advanced Test Pattern Generator IP Software API
11.1. About the Advanced Test Pattern Generator IP x
11.1.1. Advanced Test Pattern Generator IP Performance and Resources
11.3. Advanced Test Pattern Generator IP Functional Description x
11.3.1. Test Patterns 11.3.2. Dimensions, Offsets, and Alpha Settings 11.3.3. Run-time Settings 11.3.4. Advanced Test Pattern Generator IP Interfaces
12. AXI-Stream Broadcaster Intel® FPGA IP x
12.1. About the AXI-Stream Broadcaster IP 12.2. AXI-Stream Broadcaster IP Parameters 12.3. AXI-Stream Broadcaster IP Interfaces
12.1. About the AXI-Stream Broadcaster IP x
12.1.1. AXI-Stream Broadcaster IP Features 12.1.2. AXI-Stream Broadcaster IP Performance and Resources
13. Bits per Color Sample Adapter Intel FPGA IP x
13.1. About the Bits per Color Sample Adapter IP 13.2. Bits per Color Sample Adapter IP Parameters 13.3. Bits per Color Sample Adapter IP Interfaces 13.4. Bits per Color Sample Adapter IP Registers 13.5. Bits per Color Sample Adapter Software API
13.1. About the Bits per Color Sample Adapter IP x
13.1.1. Bits per Color Sample Adapter IP Performance and Resources
14. Black Level Correction Intel® FPGA IP x
14.1. About the Black Level Correction IP 14.2. Black Level Correction IP Parameters 14.3. Black Level Correction IP Functional Description 14.4. Black Level Correction IP Registers 14.5. Black Level Correction IP Software API
14.1. About the Black Level Correction IP x
14.1.1. Black Level Correction IP Performance and Resources
14.3. Black Level Correction IP Functional Description x
14.3.1. Black Level Correction IP Interfaces
15. Black Level Statistics Intel® FPGA IP x
15.1. About the Black Level Statistics IP 15.2. Black Level Statistics IP Parameters 15.3. Black Level Statistics IP Interfaces 15.4. Black Level Statistics IP Registers 15.5. Black Level Statistics IP Software API
15.1. About the Black Level Statistics IP x
15.1.1. Black Level Statistics IP Performance and Resources
16. Chroma Key Intel® FPGA IP x
16.1. About the Chroma Key IP 16.2. Chroma Key IP Parameters 16.3. Chroma Key IP Interfaces 16.4. Chroma Key Replacement 16.5. Chroma Key IP Registers 16.6. Chroma Key IP Software API
16.1. About the Chroma Key IP x
16.1.1. Chroma Key IP Performance and Resources
17. Chroma Resampler Intel® FPGA IP x
17.1. About the Chroma Resampler IP 17.2. Chroma Resampler IP Parameters 17.3. Chroma Resampler IP Functional Description 17.4. Chroma Resampler IP Registers 17.5. Chroma Resampler IP Software API
17.1. About the Chroma Resampler IP x
17.1.1. Chroma Resampler Performance and Resources
17.3. Chroma Resampler IP Functional Description x
17.3.1. Chroma Resampler IP Interfaces
18. Clipper Intel® FPGA IP x
18.1. About the Clipper IP 18.2. Clipper IP Parameters 18.3. Clipper IP Interfaces 18.4. Clipper IP Registers 18.5. Clipper IP Software API
18.1. About the Clipper IP x
18.1.1. Clipper IP Performance and Resources
19. Clocked Video Input Intel® FPGA IP x
19.1. About the Clocked Video Input IP 19.2. Initializing the Clocked Video Input IP 19.3. Clocked Video Input IP Parameters 19.4. Clocked Video Input IP Interfaces 19.5. Clocked Video Input IP Registers 19.6. Clocked Video Input IP Software API
19.1. About the Clocked Video Input IP x
19.1.1. Clocked Video Input IP Features 19.1.2. Clocked Video Input IP Performance and Resources
20. Clocked Video to Full-Raster Converter Intel® FPGA IP x
20.1. About the Clocked Video to Full-Raster Converter IP 20.2. Clocked Video to Full-Raster Converter Parameters 20.3. Clocked Video to Full-Raster Converter Block Description 20.4. Clocked Video Converter to Full-Raster IP Registers
20.1. About the Clocked Video to Full-Raster Converter IP x
20.1.1. Clocked Video to Full-Raster Converter Features 20.1.2. Clocked Video to Full-Raster Converter Performance and Resources
20.3. Clocked Video to Full-Raster Converter Block Description x
20.3.1. Clocked Video to Full-Raster Converter Interfaces
21. Clocked Video Output Intel® FPGA IP x
21.1. About the Clocked Video Output IP 21.2. Clocked Video Output IP Parameters 21.3. Clocked Video Output IP Functional Description 21.4. Clocked Video Output IP Interfaces 21.5. Clocked Video Output IP Registers 21.6. Clocked Video Output IP Software API
21.1. About the Clocked Video Output IP x
21.1.1. Clocked Video Output IP Performance and Resources 21.1.2. Clocked Video Output IP Features
22. Color Plane Manager Intel® FPGA IP x
22.1. About the Color Plane Manager IP 22.2. Color Plane Manager IP Parameters 22.3. Color Plane Manager IP Functional Description 22.4. Color Plane Manager IP Registers 22.5. Color Plane Manager Software API
22.1. About the Color Plane Manager IP x
22.1.1. Color Plane Manager IP Performance and Resources
22.3. Color Plane Manager IP Functional Description x
22.3.1. Color Plane Manager IP Interfaces
23. Color Space Converter Intel® FPGA IP x
23.1. About the Color Space Converter IP 23.2. Color Space Converter IP Parameters 23.3. Color Space Converter IP Functional Description 23.4. Color Space Converter IP Registers 23.5. Color Space Converter IP Software API
23.1. About the Color Space Converter IP x
23.1.1. Color Space Converter IP Features 23.1.2. Color Space Converter IP Performance and Resources
23.3. Color Space Converter IP Functional Description x
23.3.1. Color Space Converter IP Interfaces
24. Defective Pixel Correction Intel® FPGA IP x
24.1. About the Defective Pixel Correction IP 24.2. Defective Pixel Correction IP Parameters 24.3. Defective Pixel Correction IP Functional Description 24.4. Defective Pixel Correction IP Registers 24.5. Defective Pixel Correction IP Software API
24.1. About the Defective Pixel Correction IP x
24.1.1. Defective Pixel Correction IP Performance and Resources
24.3. Defective Pixel Correction IP Functional Description x
24.3.1. Defective Pixel Correction IP Interfaces
25. Deinterlacer Intel® FPGA IP x
25.1. About the Deinterlacer IP 25.2. Deinterlacer Parameters 25.3. Deinterlacer IP Functional Description 25.4. Deinterlacer IP Registers 25.5. Deinterlacer IP Software API
25.1. About the Deinterlacer IP x
25.1.1. Deinterlacer Performance and Resources
25.3. Deinterlacer IP Functional Description x
25.3.1. Deinterlacer Interfaces
26. Demosaic Intel® FPGA IP x
26.1. About the Demosaic IP 26.2. Demosaic IP Parameters 26.3. Demosaic IP Functional Description 26.4. Demosaic IP Registers 26.5. Demosaic IP Software API
26.1. About the Demosaic IP x
26.1.1. Demosaic IP Performance and Resources
26.3. Demosaic IP Functional Description x
26.3.1. Demosaic IP Interfaces
27. FIR Filter Intel® FPGA IP x
27.1. About the FIR Filter 27.2. FIR Filter Parameters 27.3. FIR Filter IP Operation 27.4. FIR Filter Interfaces 27.5. FIR Filter Registers 27.6. FIR Filter IP Software API
27.1. About the FIR Filter x
27.1.1. FIR Filter IP Performance and Resources
27.3. FIR Filter IP Operation x
27.3.1. FIR Filter Processing 27.3.2. FIR Filter Precision 27.3.3. FIR Coefficient Specification 27.3.4. FIR Filter Symmetry 27.3.5. Result to Output Data Type Conversion
27.3.4. FIR Filter Symmetry x
27.3.4.1. No Symmetry 27.3.4.2. Horizontal Symmetry 27.3.4.3. Vertical Symmetry 27.3.4.4. Horizontal and Vertical Symmetry 27.3.4.5. Diagonal Symmetry
28. Frame Cleaner Intel® FPGA IP x
28.1. About the Frame Cleaner IP 28.2. Frame Cleaner IP Parameters 28.3. Frame Cleaner IP Functional Description 28.4. Frame Cleaner IP Interfaces 28.5. Frame Cleaner IP Registers 28.6. Frame Cleaner IP Software API
28.1. About the Frame Cleaner IP x
28.1.1. Frame Cleaner IP Performance and Resources
29. Full-Raster to Clocked Video Converter Intel® FPGA IP x
29.1. About the Full-Raster to Clocked Video Converter 29.2. Full Raster to Clocked Video Converter Parameters 29.3. Full-Raster to Clocked Video Converter Block Description 29.4. Full-Raster to Clocked Video Converter Registers
29.1. About the Full-Raster to Clocked Video Converter x
29.1.1. Full-Raster to Clocked Video Converter Features 29.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
29.3. Full-Raster to Clocked Video Converter Block Description x
29.3.1. Full Raster to Clocked Video Converter Interfaces
30. Full-Raster to Streaming Converter Intel® FPGA IP x
30.1. About the Full-Raster to Streaming Converter IP 30.2. Full-Raster to Streaming Converter Parameters 30.3. Full-Raster to Streaming Converter Block Description
30.1. About the Full-Raster to Streaming Converter IP x
30.1.1. Full-Raster to Streaming Converter Features 30.1.2. Full-Raster to Streaming Converter Performance and Resources
30.3. Full-Raster to Streaming Converter Block Description x
30.3.1. Full-Raster to Streaming Converter Interfaces
31. Genlock Controller Intel® FPGA IP x
31.1. About the Genlock Controller IP 31.2. Genlock Controller IP Parameters 31.3. Genlock Controller IP Functional Description 31.4. Using Genlock Controller IP Software 31.5. Genlock Controller IP Registers 31.6. Genlock Controller IP Software API
31.1. About the Genlock Controller IP x
31.1.1. Genlock Controller IP Performance and Resources
31.3. Genlock Controller IP Functional Description x
31.3.1. Genlock Controller IP Interfaces
31.4. Using Genlock Controller IP Software x
31.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 31.4.3. Setting the VCXO hold over 31.4.4. Restarting the Genlock Controller IP 31.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 31.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 31.4.7. Disturbing a Reference Clock (a cable pull)
32. Generic Crosspoint Intel® FPGA IP x
32.1. About the Generic Crosspoint IP 32.2. Generic Crosspoint IP Parameters 32.3. Generic Crosspoint IP Interfaces 32.4. Generic Crosspoint IP Registers 32.5. Generic Crosspoint IP Software API
32.1. About the Generic Crosspoint IP x
32.1.1. Generic Crosspoint IP Features 32.1.2. Generic Crosspoint Performance and Resources
33. Genlock Signal Router Intel® FPGA IP x
33.1. About the Genlock Signal Router IP 33.2. Genlock Signal Router IP Parameters 33.3. Genlock Signal Router IP Interfaces 33.4. Genlock Signal Router IP Registers 33.5. Genlock Signal Router IP Software API
33.1. About the Genlock Signal Router IP x
33.1.1. Genlock Signal Router IP Features 33.1.2. Genlock Signal Router IP Performance and Resources
34. Guard Bands Intel® FPGA IP x
34.1. About the Guard Bands IP 34.2. Guard Bands IP Parameters 34.3. Guard Bands IP Interfaces 34.4. Guard Bands IP Registers 34.5. Guard Bands IP Software API
34.1. About the Guard Bands IP x
34.1.1. Guard Bands IP Performance and Resources
35. Histogram Statistics Intel® FPGA IP x
35.1. About the Histogram Statistics IP 35.2. Histogram Statistics IP Parameters 35.3. Histogram Statistics IP Interfaces 35.4. Histogram Statistics IP Registers 35.5. Histogram Statistics IP Software API
35.1. About the Histogram Statistics IP x
35.1.1. Histogram Statistics IP Performance and Resources
36. Interlacer Intel® FPGA IP x
36.1. About the Interlacer IP 36.2. Interlacer IP Parameters 36.3. Interlacer IP Functional Description 36.4. Interlacer IP Registers 36.5. Interlacer IP Software API
36.1. About the Interlacer IP x
36.1.1. Interlacer IP Performance and Resources
36.3. Interlacer IP Functional Description x
36.3.1. Interlacer IP Interfaces
37. Mixer Intel® FPGA IP x
37.1. About the Mixer IP 37.2. Mixer IP Parameters 37.3. Mixer IP Functional Description 37.4. Mixer IP Registers 37.5. Mixer IP Software API
37.1. About the Mixer IP x
37.1.1. Mixer IP Performance and Resources
37.3. Mixer IP Functional Description x
37.3.1. Mixer IP Interfaces
38. Pixels in Parallel Converter Intel® FPGA IP x
38.1. About the Pixels in Parallel Converter IP 38.2. Pixels in Parallel Converter IP Parameters 38.3. Pixels in Parallel Converter Interfaces 38.4. Pixels in Parallel Converter Registers 38.5. Pixels in Parallel Converter IP Software API
38.1. About the Pixels in Parallel Converter IP x
38.1.1. Pixels in Parallel Converter IP Performance and Resources
39. Scaler Intel® FPGA IP x
39.1. About the Scaler 39.2. Scaler IP Parameters 39.3. Scaler IP Functional Description 39.4. Scaler IP Registers 39.5. Scaler IP Software API
39.1. About the Scaler x
39.1.1. Scaler IP Performance and Resources
39.2. Scaler IP Parameters x
39.2.1. Scaler Maximum Resolution
39.3. Scaler IP Functional Description x
39.3.1. Coefficient Selection 39.3.2. Coefficient Quantization 39.3.3. Filter Behavior at Edge Boundaries 39.3.4. Partial Frame Scaling 39.3.5. 422 and 420 Chroma Sampled Data Scaling 39.3.6. Scaler IP Interfaces
39.3.1. Coefficient Selection x
39.3.1.1. Updating Scaler IP Runtime Coefficients
40. Stream Cleaner Intel® FPGA IP x
40.1. About the Stream Cleaner IP 40.2. Stream Cleaner IP Parameters 40.3. Stream Cleaner IP Functional Description
40.1. About the Stream Cleaner IP x
40.1.1. Stream Cleaner IP Performance and Resources
40.3. Stream Cleaner IP Functional Description x
40.3.1. Stream Cleaner IP Interfaces
41. Switch Intel® FPGA IP x
41.1. About the Switch IP 41.2. Switch IP Parameters 41.3. Switch IP Functional Description 41.4. Switch IP Registers 41.5. Switch IP Software API
41.1. About the Switch IP x
41.1.1. Switch IP Performance and Resources
41.3. Switch IP Functional Description x
41.3.1. Switch IP Latency 41.3.2. Switch IP Interfaces
42. Tone Mapping Operator Intel® FPGA IP x
42.1. About the Tone Mapping Operator IP 42.2. TMO IP Parameters 42.3. TMO IP Block Description 42.4. TMO IP Registers 42.5. TMO IP Software API
42.1. About the Tone Mapping Operator IP x
42.1.1. TMO IP Features 42.1.2. TMO IP Performance and Resource Utilization
42.3. TMO IP Block Description x
42.3.1. TMO IP Interfaces 42.3.2. TMO IP Latency
43. Test Pattern Generator Intel® FPGA IP x
43.1. About the Test Pattern Generator IP 43.2. Test Pattern Generator IP Parameters 43.3. Test Pattern Generator IP Functional Description 43.4. Test Pattern Generator IP Registers 43.5. Test Pattern Generator IP Software API
43.1. About the Test Pattern Generator IP x
43.1.1. Test Pattern Generator IP Performance and Resources
43.3. Test Pattern Generator IP Functional Description x
43.3.1. Test Patterns 43.3.2. Output Subsampling and Color Space 43.3.3. Run-time Settings 43.3.4. Test Pattern Generator IP Interfaces
44. Unsharp Mask Intel® FPGA IP x
44.1. About the Unsharp Mask IP 44.2. Unsharp Mask IP Parameters 44.3. Unsharp Mask IP Functional Description 44.4. Unsharp Mask IP Registers 44.5. Unsharp Mask IP Software API
44.1. About the Unsharp Mask IP x
44.1.1. Unsharp Mask IP Performance and Resources
44.3. Unsharp Mask IP Functional Description x
44.3.1. Unsharp Mask IP Interfaces
45. Video and Vision Monitor Intel FPGA IP x
45.1. About the Video and Vision Monitor IP 45.2. Video and Vision Monitor IP Parameters 45.3. Video and Vision Monitor IP Functional Description 45.4. Video and Vision Monitor IP Registers 45.5. Video and Vision Monitor Software API
45.1. About the Video and Vision Monitor IP x
45.1.1. Video and Vision Monitor IP Performance and Resources
45.3. Video and Vision Monitor IP Functional Description x
45.3.1. Video and Vision Monitor IP Interfaces
46. Video Frame Buffer Intel® FPGA IP x
46.1. About the Video Frame Buffer IP 46.2. Video Frame Buffer IP Parameters 46.3. Video Frame Buffer IP Functional Description 46.4. Video Frame Buffer IP Registers 46.5. Video Frame Buffer IP Software API
46.1. About the Video Frame Buffer IP x
46.1.1. Video Frame Buffer Performance and Resources
46.3. Video Frame Buffer IP Functional Description x
46.3.1. Video Frame Buffer IP Interfaces
47. Video Frame Reader Intel FPGA IP x
47.1. About the Video Frame Reader IP 47.2. Video Frame Reader IP Parameters 47.3. Video Frame Reader IP Functional Description 47.4. Video Frame Reader IP Registers 47.5. Video Frame Reader IP Software API
47.1. About the Video Frame Reader IP x
47.1.1. Video Frame Reader IP Performance and Resources
47.3. Video Frame Reader IP Functional Description x
47.3.1. Video Frame Reader IP Interfaces
48. Video Frame Writer Intel FPGA IP x
48.1. About the Video Buffer Writer IP 48.2. Video Frame Writer IP Parameters 48.3. Video Frame Writer IP Functional Description 48.4. Video Frame Writer IP Registers 48.5. Video Frame Writer IP Software API
48.1. About the Video Buffer Writer IP x
48.1.1. Video Frame Writer IP Performance and Resources
48.3. Video Frame Writer IP Functional Description x
48.3.1. Video Frame Writer IP Interfaces
49. Video Streaming FIFO Intel® FPGA IP x
49.1. About the Video Streaming FIFO IP 49.2. Video Streaming FIFO IP Parameters 49.3. Video Streaming FIFO IP Interfaces
49.1. About the Video Streaming FIFO IP x
49.1.1. Video Streaming FIFO IP Performance and Resources
50. Video Timing Generator Intel® FPGA IP x
50.1. About the Video Timing Generator IP 50.2. Video Timing Generator IP Parameters 50.3. Video Timing Generator IP Functional Description 50.4. Video Timing Generator IP Interfaces 50.5. Video Timing Generator IP Registers 50.6. Video Timing Generator IP Software API
50.1. About the Video Timing Generator IP x
50.1.1. Video Timing Generator IP Features 50.1.2. Video Timing Generator IP Performance and Resources
51. Vignette Correction Intel® FPGA IP x
51.1. About the Vignette Correction IP 51.2. Vignette Correction IP Parameters 51.3. Vignette Correction IP Interfaces 51.4. Vignette Correction IP Registers 51.5. Vignette Correction IP Software API
51.1. About the Vignette Correction IP x
51.1.1. Vignette Correction IP Performance and Resources
52. Warp Intel® FPGA IP x
52.1. About the Warp IP 52.2. Warp IP Parameters 52.3. Warp IP Block Description 52.4. Warp IP Registers 52.5. Warp IP Software API
52.1. About the Warp IP x
52.1.1. Warp IP Features 52.1.2. Warp IP Performance and Resource Utilization
52.3. Warp IP Block Description x
52.3.1. Block Cache Tool 52.3.2. Warp IP Interfaces 52.3.3. Warp IP Latency 52.3.4. External Memory for Warp IP
52.5. Warp IP Software API x
52.5.1. Using Warp IP Software 52.5.2. Warp IP Software Code Examples
53. White Balance Correction Intel® FPGA IP x
53.1. About the White Balance Correction IP 53.2. White Balance Correction IP Parameters 53.3. White Balance Correction IP Functional Description 53.4. White Balance Correction IP Registers 53.5. White Balance Correction IP Software API
53.1. About the White Balance Correction IP x
53.1.1. White Balance Correction IP Performance and Resources
53.3. White Balance Correction IP Functional Description x
53.3.1. White Balance Correction IP Interfaces
54. White Balance Statistics Intel® FPGA IP x
54.1. About the White Balance Statistics IP 54.2. White Balance Statistics IP Parameters 54.3. White Balance Statistics IP Interfaces 54.4. White Balance Statistics IP Registers 54.5. White Balance Statistics IP Software API
54.1. About the White Balance Statistics IP x
54.1.1. White Balance Statistics IP Performance and Resources
55. Design Security x
55.1. Memory Subsystems 55.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. Adaptive Noise Reduction Intel® FPGA IP
11. Advanced Test Pattern Generator Intel® FPGA IP
12. AXI-Stream Broadcaster Intel® FPGA IP
13. Bits per Color Sample Adapter Intel FPGA IP
14. Black Level Correction Intel® FPGA IP
15. Black Level Statistics Intel® FPGA IP
16. Chroma Key Intel® FPGA IP
17. Chroma Resampler Intel® FPGA IP
18. Clipper Intel® FPGA IP
19. Clocked Video Input Intel® FPGA IP
20. Clocked Video to Full-Raster Converter Intel® FPGA IP
21. Clocked Video Output Intel® FPGA IP
22. Color Plane Manager Intel® FPGA IP
23. Color Space Converter Intel® FPGA IP
24. Defective Pixel Correction Intel® FPGA IP
25. Deinterlacer Intel® FPGA IP
26. Demosaic Intel® FPGA IP
27. FIR Filter Intel® FPGA IP
28. Frame Cleaner Intel® FPGA IP
29. Full-Raster to Clocked Video Converter Intel® FPGA IP
30. Full-Raster to Streaming Converter Intel® FPGA IP
31. Genlock Controller Intel® FPGA IP
32. Generic Crosspoint Intel® FPGA IP
33. Genlock Signal Router Intel® FPGA IP
34. Guard Bands Intel® FPGA IP
35. Histogram Statistics Intel® FPGA IP
36. Interlacer Intel® FPGA IP
37. Mixer Intel® FPGA IP
38. Pixels in Parallel Converter Intel® FPGA IP
39. Scaler Intel® FPGA IP
40. Stream Cleaner Intel® FPGA IP
41. Switch Intel® FPGA IP
42. Tone Mapping Operator Intel® FPGA IP
43. Test Pattern Generator Intel® FPGA IP
44. Unsharp Mask Intel® FPGA IP
45. Video and Vision Monitor Intel FPGA IP
46. Video Frame Buffer Intel® FPGA IP
47. Video Frame Reader Intel FPGA IP
48. Video Frame Writer Intel FPGA IP
49. Video Streaming FIFO Intel® FPGA IP
50. Video Timing Generator Intel® FPGA IP
51. Vignette Correction Intel® FPGA IP
52. Warp Intel® FPGA IP
53. White Balance Correction Intel® FPGA IP
54. White Balance Statistics Intel® FPGA IP
55. Design Security
56. Document Revision History for Video and Vision Processing Suite User Guide

39.5. Scaler IP Software API

The IP includes software for run-time control. The IP does not fit any of the generic device models provided by the Nios II HAL and it exposes a set of dedicated accessors to the control and status registers. The IP driver structure inherits the base driver structure so all common methods defined in Video and Vision Processing IPs Software API are applicable.

Register definition header file: intel_vvp_scaler_regs.h

Include file: intel_vvp_scaler.h

Table 739.  Scaler IP Software API
Name Description
intel_vvp_scaler_init Initialize the Scaler instance
Intel_vvp_core_* .Accessors defined in Video and Vision Processing IPs Software Programming Model . Writable when Lite is on. Readable when Lite is off and Debug features is on.
intel_vvp_scaler_get_lite_mode Returns if Lite mode is on
intel_vvp_scaler_get_debug_enabled Returns if Debug features is on

intel_vvp_scaler_get_pixels_in_parallel

Returns the number of pixels transmitted in parallel (per valid beat)

intel_vvp_scaler_get_max_input_width

Returns the maximum input width supported

intel_vvp_scaler_get_max_output_width

Returns the maximum output width supported
intel_vvp_scaler_get_scaling_algorithm Returns the scaling algorithm
intel_vvp_scaler_is_coeffs_loading_enabled Returns if the scaling coefficients can be loaded/updated at run-time
intel_vvp_scaler_are_coeffs_preinitialized Returns if the scaling coefficients are automatically initialized with default values out of reset
intel_vvp_scaler_is_vertical_scaling_enabled Returns if the IP can do vertical scaling
Intel_vvp_scaler_is_partial_vertical_scaling_enabled

Returns if the IP can do split vertical scaling

intel_vvp_scaler_get_num_vertical_taps Returns the number of vertical taps
intel_vvp_scaler_get_num_vertical_phases Returns the number of vertical phases
intel_vvp_scaler_get_num_vertical_banks Returns the number of vertical banks
intel_vvp_scaler_are_vertical_coeffs_signed Returns if the vertical scaling coefficients have a sign bit and can be negative

intel_vvp_scaler_get_vertical_coeffs_int_bits

Returns the number of integer bits (excluding sign bit) available to quantize the vertical scaling coefficients

intel_vvp_scaler_get_vertical_coeffs_frac_bits

Returns the number of fractional bits available to quantize the vertical scaling coefficients
intel_vvp_scaler_is_horizontal_scaling_enabled Returns if the IP can do horizontal scaling
intel_vvp_scaler_is_partial_horizontal_scaling_enabled Returns if the IP can do split horizontal scaling
intel_vvp_scaler_get_num_horizontal_taps Returns the number of horizontal taps
intel_vvp_scaler_get_num_horizontal_phases Returns the number of horizontal phases
intel_vvp_scaler_get_num_horizontal_banks Returns the number of horizontal banks
intel_vvp_scaler_are_ horizontal_coeffs_signed Returns if the horizontal scaling coefficients have a sign bit and can be negative

intel_vvp_scaler_get_ horizontal_coeffs_int_bits

Returns the number of integer bits (excluding sign bit) available to quantize the horizontal scaling coefficients

intel_vvp_scaler_get_ horizontal_coeffs_frac_bits

Returns the number of fractional bits available to quantize the horizontal scaling coefficients
intel_vvp_scaler_get_rounding_method Returns the method used to convert floating-point values back to integer values at the output of the IP
intel_vvp_scaler_is_running Returns if the IP is currently processing video data
intel_vvp_scaler_get_commit_status Returns if there are uncommitted writes
intel_vvp_scaler_get_status Reads the status register
intel_vvp_scaler_set_output_width Selects the output width
intel_vvp_scaler_set_total_input_width

Selects the full image input width (split scaling only)

intel_vvp_scaler_set_total_output_width

Selects the full image output width (split scaling only)

intel_vvp_scaler_set_output_height Selects the output height
intel_vvp_scaler_set_total_input_height

Selects the full image input height (split scaling only)

intel_vvp_scaler_set_total_output_height

Selects the full image output height (split scaling only)

intel_vvp_scaler_set_h_pos_error

Selects the horizontal offset error (split scaling only)

intel_vvp_scaler_set_v_pos_error

Selects the vertical offset error (split scaling only)

intel_vvp_scaler_set_h_extended_fill

Enables horizontal split extension (split scaling only)

intel_vvp_scaler_set_v_extended_fill

Enables vertical split extension (split scaling only)

intel_vvp_scaler_set_h_phase_offset_error

Selects the horizontal phase offset (split scaling only)

intel_vvp_scaler_set_v_phase_offset_error

Selects the vertical phase offset (split scaling only)

intel_vvp_scaler_set_split_h_scaling

Setup the scaler for a horizontal split scaling

intel_vvp_scaler_set_split_v_scaling

Setup the scaler for a vertical split scaling

intel_vvp_scaler_set_v_bank Selects the vertical coefficients bank for the next commit
intel_vvp_scaler_set_h_bank Selects the horizontal coefficients bank for the next commit
intel_vvp_scaler_get_output_width Returns the last selected output width
intel_vvp_scaler_get_total_input_width

Returns the last selected full image input width (split scaling)

intel_vvp_scaler_get_total_output_width

Returns the last selected full image output width (split scaling)

intel_vvp_scaler_get_output_height Returns the last selected output height
intel_vvp_scaler_get_total_input_height

Returns the last selected full image input height (split scaling)

intel_vvp_scaler_get_total_output_height

Returns the last selected full image output height (split scaling)

intel_vvp_scaler_get_h_pos_error

Returns the last selected horizontal offset error (split scaling)

intel_vvp_scaler_get_v_pos_error

Returns the last selected vertical offset error (split scaling)

intel_vvp_scaler_get_h_extended_fill

Returns if horizontal split extension is enabled (split scaling only)
intel_vvp_scaler_get_v_extended_fill

Returns if vertical split extension is enabled (split scaling only)
intel_vvp_scaler_get_ h_phase_offset_error

Returns the last selected horizontal phase offset and error (split scaling)

intel_vvp_scaler_get_ v_phase_offset_error Returns the last selected vertical phase offset and error (split scaling)
intel_vvp_scaler_get_v_bank Returns the last selected vertical coefficients bank
intel_vvp_scaler_get_h_bank Returns the last selected horizontal coefficients bank
intel_vvp_scaler_set_quantized_coeffs Program the IP with a new set of quantized coefficients for a specified phase
intel_vvp_scaler_set_coeffs Program the IP with a new set of floating-point coefficients for a specified phase
intel_vvp_scaler_commit_writes Commit all outstanding writes

enum eIntelVvpScalerAlgorithms

Members

kIntelVvpScalerNearestNeighborScaling (0) – Nearest neighbor scaling

kIntelVvpScalerBilinearScaling (1) – Bilinear scaling

kIntelVvpScalerPolyphaseScaling (2) – Polyphase scaling

kIntelVvpScalerInvalidScalingAlgo (-1) – Invalid scaling algorithm (used to indicate errors)

Description

Enumeration for the configurable scaling algorithms

intel_vvp_scaler_init

Prototype 
int intel_vvp_scaler_init(intel_vvp_scaler_instance *instance, intel_vvp_core_base base);
Description

Initializes a Scaler instance. The initialization stops early if the vendor ID or product ID read at the base address are not a match or if the register map version is not supported. Otherwise, the function proceeds to read and store the IP compile-time parameterization. The instance is not fully initialized and the application should not use it further if returning a non-zero error code.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

base – base address of the register map

Returns

kIntelVvpCoreOk (0) in case of success, a negative error code in case of error

kIntelVvpCoreVidErr if the vendor id of the core is not the IntelFPGA vendor ID (0x6AF7).

kIntelVvpCorePidErr if the product_id does not match with the Scaler product ID

kIntelVvpCoreInstanceErr if the instance is a null pointer

kIntelVvpScalerMapVersionErr if the register map is not supported

intel_vvp_scaler_get_lite_mode

Prototype 
bool intel_vvp_scaler_get_lite_mode(intel_vvp_scaler_instance *instance);
Description

Returns the value of the LITE_MODE register. The instance must be a valid intel_vvp_scaler_instance fully initialized

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

true if the IP is parameterized in lite mode

intel_vvp_scaler_get_debug_enabled

Prototype 
 bool intel_vvp_scaler_get_debug_enabled(intel_vvp_scaler_instance *instance);
Description

Returns the value of the DEBUG_ENABLED register. The instance must be a valid intel_vvp_scaler_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

true if the IP is parameterized with debug features enabled

intel_vvp_scaler_get_pixels_in_parallel

Prototype 
 uint8_t intel_vvp_scaler_get_pixels_in_parallel(intel_vvp_scaler_instance *instance);
Description

Returns the value of the PIXELS_IN_PARALLEL register. The instance must be a valid intel_vvp_scaler_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

the pixel in parallel parameter (pixels transmitted per beat/clock cycle) used to generate the IP.

intel_vvp_scaler_get_max_input_width

Prototype 
 uint32_t intel_vvp_scaler_get_max_input_width(intel_vvp_scaler_instance *instance);
Description

Returns the value of the MAX_INPUT_WIDTH register. The instance must be a valid intel_vvp_scaler_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

the maximum input width supported by the IP

intel_vvp_scaler_get_max_output_width

Prototype 
 uint32_t intel_vvp_scaler_get_max_output_width(intel_vvp_scaler_instance *instance);
Description

Returns the value of the MAX_OUTPUT_WIDTH register. The instance must be a valid intel_vvp_scaler_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

the maximum output width supported by the IP

intel_vvp_scaler_get_scaling_algorithm

Prototype 
 eIntelVvpScalerAlgorithms intel_vvp_scaler_get_scaling_algorithm(intel_vvp_scaler_instance* instance);
Description

Returns the value of the SCALER_ALGORITHM register. The instance must be a valid intel_vvp_scaler_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

The scaling algorithm the IP is configured with

intel_vvp_scaler_is_coeffs_loading_enabled

Prototype 
 bool intel_vvp_scaler_is_coeffs_loading_enabled(intel_vvp_scaler_instance* instance);
Description

Returns the value of the COEFFS_RUNTIME_LOAD register. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for polyphase scaling

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

If the IP is configured to support run-time reloading of coefficients

intel_vvp_scaler_are_coeffs_preinitialized

Prototype 
 bool intel_vvp_scaler_are_coeffs_preinitialized(intel_vvp_scaler_instance* instance);
Description

Returns the value of the COEFFS_MEM_INIT register. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for polyphase scaling

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

If the IP is configured to start with initialized coefficients

intel_vvp_scaler_is_vertical_scaling_enabled

Prototype 
 bool intel_vvp_scaler_is_vertical_scaling_enabled (intel_vvp_scaler_instance* instance);
Description

Returns the value of the V_SCALING_ENABLED register. The instance must be a valid intel_vvp_scaler_instance fully initialized

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

If the IP is configured to perform vertical scaling

intel_vvp_scaler_is_partial_vertical_scaling_enabled

Prototype 
bool intel_vvp_scaler_is_partial_vertical_scaling_enabled (intel_vvp_scaler_instance* instance);
Description

Returns the value of the V_PARTIAL_SCALING_ENABLED register. The instance must be a valid intel_vvp_scaler_instance fully initialized

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

If the IP is configured to perform split vertical scaling

intel_vvp_scaler_get_num_vertical_taps

Prototype 
 uint8_t intel_vvp_scaler_get_num_vertical_taps(intel_vvp_scaler_instance* instance);
Description

Returns the value of the V_NUM_TAPS register. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for vertical scaling

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

The number of taps used for vertical scaling

intel_vvp_scaler_get_num_vertical_phases

Prototype 
 uint16_t intel_vvp_scaler_get_num_vertical_phases(intel_vvp_scaler_instance* instance);
Description

Returns the value of the V_NUM_PHASES register. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for vertical scaling

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

The number of taps used for vertical scaling

intel_vvp_scaler_get_num_vertical_banks

Prototype 
 uint8_t intel_vvp_scaler_get_num_vertical_banks(intel_vvp_scaler_instance* instance);
Description

Returns the value of the V_NUM_BANKS register. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for vertical polyphase scaling

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

The number of coefficient banks available for vertical scaling

intel_vvp_scaler_are_vertical_coeffs_signed

Prototype 
 bool intel_vvp_scaler_are_coeffs_signed(intel_vvp_scaler_instance* instance);
Description

Returns the value of the V_COEFFS_SIGNED register. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for vertical polyphase scaling

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

If signed coefficients have been enabled for vertical scaling at IP generation time

intel_vvp_scaler_get_vertical_coeffs_int_bits

Prototype 
 uint8_t intel_vvp_scaler_get_coeffs_int_bits (intel_vvp_scaler_instance *instance);
Description

Returns the value of the V_COEFFS_INT_BITS register. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for vertical polyphase scaling

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

the number of integer bits, excluding sign bit, set at IP generation time to parameterize the quantization of the vertical scaling coefficients

intel_vvp_scaler_get_vertical_coeffs_frac_bits

Prototype 
 uint8_t intel_vvp_scaler_get_vertical_coeffs_frac_bits (intel_vvp_scaler_instance *instance);
Description

Returns the value of the V_COEFFS_FRAC_BITS register. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for vertical polyphase scaling

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

the number of fractional bits set at IP generation time to parameterize the quantization of the vertical scaling coefficients

intel_vvp_scaler_is_horizontal_scaling_enabled

Prototype 
 bool intel_vvp_scaler_is_horizontal_scaling_enabled (intel_vvp_scaler_instance* instance);
Description

Returns the value of the H_SCALING_ENABLED register. The instance must be a valid intel_vvp_scaler_instance fully initialized

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

If the IP is configured to perform horizontal scaling

intel_vvp_scaler_is_partial_horizontal_scaling_enabled

Prototype

bool intel_vvp_scaler_is_partial_horizontal_scaling_enabled (intel_vvp_scaler_instance* instance);

Description

Returns the value of the H_PARTIAL_SCALING_ENABLED register. The instance must be a valid intel_vvp_scaler_instance fully initialized

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

If the IP is configured to perform split horizontal scaling

intel_vvp_scaler_get_num_horizontal_taps

Prototype 
 uint8_t intel_vvp_scaler_get_num_horizontal_taps(intel_vvp_scaler_instance* instance);
Description

Returns the value of the H_NUM_TAPS register. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for horizontal scaling

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

The number of taps used for horizontal scaling

intel_vvp_scaler_get_num_horizontal_phases

Prototype 
 uint16_t intel_vvp_scaler_get_num_horizontal_phases(intel_vvp_scaler_instance* instance);
Description

Returns the value of the H_NUM_PHASES register. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for horizontal scaling

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

The number of taps used for horizontal scaling

intel_vvp_scaler_get_num_horizontal_banks

Prototype 
 uint8_t intel_vvp_scaler_get_num_horizontal_banks(intel_vvp_scaler_instance* instance);
Description

Returns the value of the H_NUM_BANKS register. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for horizontal polyphase scaling

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

The number of coefficient banks available for horizontal scaling

intel_vvp_scaler_are_horizontal_coeffs_signed

Prototype 
 bool intel_vvp_scaler_are_coeffs_signed(intel_vvp_scaler_instance* instance);
Description

Returns the value of the H_COEFFS_SIGNED register. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for horizontal polyphase scaling

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

If signed coefficients have been enabled for horizontal scaling at IP generation time

intel_vvp_scaler_get_horizontal_coeffs_int_bits

Prototype 
 uint8_t intel_vvp_scaler_get_coeffs_int_bits (intel_vvp_scaler_instance *instance);
Description

Returns the value of the H_COEFFS_INT_BITS register. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for horizontal polyphase scaling

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

the number of integer bits, excluding sign bit, set at IP generation time to parameterize the quantization of the horizontal scaling coefficients

intel_vvp_scaler_get_horizontal_coeffs_frac_bits

Prototype 
 uint8_t intel_vvp_scaler_get_horizontal_coeffs_frac_bits (intel_vvp_scaler_instance *instance);
Description

Returns the value of the H_COEFFS_FRAC_BITS register. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for horizontal polyphase scaling

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

the number of fractional bits set at IP generation time to parameterize the quantization of the horizontal scaling coefficients

intel_vvp_scaler_is_running

Prototype 
 bool intel_vvp_scaler_is_running(intel_vvp_scaler_instance* instance);
Description

Reads and returns the running bit of the STATUS register. The instance must be a valid intel_vvp_scaler_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

True is the IP is currently receiving/storing an input field, false when between two input fields

intel_vvp_scaler_get_commit_status

Prototype 
 bool intel_vvp_scaler_get_commit_status(intel_vvp_scaler_instance* instance);
Description

Reads and returns the commit pending bit of the STATUS register. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured in full mode.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

True is the IP is configured in full mode and if the agent interface contains uncommitted writes.

intel_vvp_scaler_get_status

Prototype 
 uint32_t intel_vvp_scaler_get_status(intel_vvp_scaler_instance* instance);
Description

Reads the STATUS register. The instance must be a valid intel_vvp_scaler_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

The content of the STATUS register

intel_vvp_scaler_set_output_width

Prototype 
 int intel_vvp_scaler_set_output_width(intel_vvp_scaler_instance *instance, uint32_t output_width)
Description

Selects the new output width. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for horizontal scaling. Also, the output width must be within the allowed range.

If split horizontal scaling is enabled, consider using intel_vvp_scaler_set_split_h_scaling to set up the scaler for split horizontal scaling rather than modifying individual registers manually.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

output_width – new output width in the range [1..max_h_width-1] where max_h_width is the maximum configured output_width returned by intel_vvp_scaler_get_max_output_width

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or not configured for horizontal scaling

kIntelVvpScalerParameterErr if the new output width is out-of-range

intel_vvp_scaler_set_total_input_width

Prototype 
int intel_vvp_scaler_set_total_input_width(intel_vvp_scaler_instance *instance, uint32_t total_input_width)
Description

Selects the new total input width. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split horizontal scaling. Consider using intel_vvp_scaler_set_split_h_scaling to set up the scaler for split horizontal scaling rather than modifying individual registers manually.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

total_input_width – new width of the full input image

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or not configured for split horizontal scaling

kIntelVvpScalerParameterErr if the new input width is invalid

intel_vvp_scaler_set_total_output_width

Prototype 
int intel_vvp_scaler_set_total_output_width(intel_vvp_scaler_instance *instance, uint32_t total_output_width)
Description

Selects the new total output width. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split horizontal scaling. Consider using intel_vvp_scaler_set_split_h_scaling to set up the scaler for split horizontal scaling rather than modifying individual registers manually.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

total_output_width – new width of the full output image

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or not configured for split horizontal scaling

kIntelVvpScalerParameterErr if the new output width is invalid

intel_vvp_scaler_set_output_height

Prototype 
 int intel_vvp_scaler_set_output_height(intel_vvp_scaler_instance *instance, uint32_t output_height)
Description

Selects the new output height. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for vertical scaling. If split vertical scaling is enabled, consider using intel_vvp_scaler_set_split_v_scaling to set up the scaler for split vertical scaling rather than modifying individual registers manually.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

output_height – new output height

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or not configured for vertical scaling

kIntelVvpScalerParameterErr if the new output height is invalid

intel_vvp_scaler_set_total_input_height

Prototype 
int intel_vvp_scaler_set_total_input_height(intel_vvp_scaler_instance *instance, uint32_t total_input_height)
Description

Selects the new total input height. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split vertical scaling. Consider using intel_vvp_scaler_set_split_v_scaling to set up the scaler for split vertical scaling rather than modifying individual registers manually.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

total_input_height – new height of the full input image

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or not configured for split vertical scaling

kIntelVvpScalerParameterErr if the new input height is invalid

intel_vvp_scaler_set_total_output_height

Prototype 
int intel_vvp_scaler_set_total_output_height(intel_vvp_scaler_instance *instance, uint32_t total_output_height)
Description

Selects the new total output height. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split vertical scaling. Consider using intel_vvp_scaler_set_split_v_scaling to set up the scaler for split vertical scaling rather than modifying individual registers manually.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

total_output_height – new height of the full output image

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or not configured for split vertical scaling

kIntelVvpScalerParameterErr if the new output height is invalid

intel_vvp_scaler_set_h_pos_error

Prototype 
int intel_vvp_scaler_set_h_pos_error(intel_vvp_scaler_instance *instance, uint32_t h_pos_error)
Description

Selects the new horizontal position error. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split horizontal scaling. Consider using intel_vvp_scaler_set_split_h_scaling to set up the scaler for split horizontal scaling rather than modifying individual registers manually.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

h_pos_error – new horizontal position error

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or not configured for split horizontal scaling

intel_vvp_scaler_set_v_pos_error

Prototype

int intel_vvp_scaler_set_v_pos_error(intel_vvp_scaler_instance *instance, uint32_t v_pos_error)

Description

Selects the new vertical position error. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split vertical scaling. Consider using intel_vvp_scaler_set_split_v_scaling to set up the scaler for split vertical scaling rather than modifying individual registers manually.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

v_pos_error – new vertical position error

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or not configured for split vertical scaling

intel_vvp_scaler_set_h_extended_fill

Prototype 
int intel_vvp_scaler_set_h_extended_fill(intel_vvp_scaler_instance *instance, bool extended_fill)
Description

Enables horizontal extension for split scaling. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split horizontal scaling. Consider using

intel_vvp_scaler_set_split_h_scaling to set up the scaler for split horizontal scaling rather than modifying individual registers manually.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

extended_fill – if horizontal split extension is enabled

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or not configured for split horizontal scaling

intel_vvp_scaler_set_v_extended_fill

Prototype 
int intel_vvp_scaler_set_v_extended_fill(intel_vvp_scaler_instance *instance, bool extended_fill)
Description

Enables vertical extension for split scaling. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split vertical scaling. Consider using intel_vvp_scaler_set_split_v_scaling to set up the scaler for split vertical scaling rather than modifying individual registers manually.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

extended_fill – if vertical split extension is enabled

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or not configured for split vertical scaling

intel_vvp_scaler_set_h_phase_offset_error

Prototype 
int intel_vvp_scaler_set_h_phase_offset_error(intel_vvp_scaler_instance *instance, uint32_t phase_offset, uint32_t phase_error);
Description

Sets the phase offset and phase offset error for split horizontal scaling. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split horizontal scaling. Consider using intel_vvp_scaler_set_split_h_scaling to set up the scaler for split horizontal scaling rather than modifying individual registers manually.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

phase_offset – new phase offset

phase_error – new phase offset error

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or not configured for split horizontal scaling

intel_vvp_scaler_set_v_phase_offset_error

Prototype 
int intel_vvp_scaler_set_v_phase_offset_error(intel_vvp_scaler_instance *instance, uint32_t phase_offset, uint32_t phase_error);
Description

Sets the phase offset and phase offset error for split vertical scaling. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split vertical scaling. Consider using intel_vvp_scaler_set_split_v_scaling to set up the scaler for split vertical scaling rather than modifying individual registers manually.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

phase_offset – new phase offset

phase_error – new phase offset error

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or not configured for split vertical scaling

intel_vvp_scaler_set_split_h_scaling

Prototype 
int intel_vvp_scaler_set_split_h_scaling(intel_vvp_scaler_instance *instance, uint32_t total_input_width, uint32_t total_output_width, uint32_t split_output_width, uint32_t split_output_left_offset, bool extended_fill, uint32_t *split_input_width, uint32_t *split_input_left_offset);
Description

This function sets the scaler for split horizontal scaling. Specify the full width of the input image, the full width of the desired output image and the required offset/width of the output split to set up the scaler to generate the given output band. Optionally, the function returns the offset and width of the corresponding band in the input image. This should be used to configure the upstream video processing pipeline and stream the correct video portion into the scaler. This call does not update the input width image info register in Lite mode. intel_vvp_core_set_img_info_width should still be called, presumably using the split_input_width value returned here as a parameter.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

total_input_width – new width of the full input image

total_output_width – new width of the full output image

split_output_width – width of the scaled split (at the output)

split_output_left_offset – left offset of the scaled split (at the output)

extended_fill – if the input split should contain extra columns of pixels on the left and/or right to ensure the output splits can be stitched with a joint that is not noticeable

split_input_width – the recommended width for the input split. The value is computed and returned by this call (optional, may be NULL)

split_input_left_offset – the recommended left offset for the input split respective to the full input image. The value is computed and returned by this call (optional, may be NULL)

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or not configured for split horizontal scaling

kIntelVvpScalerParameterErr, if one of the dimensions is invalid or if the split output width is larger than allowed by the configuration.

kIntelVvpScalerParameterErr, if the width and left offset of the output split go out-of-range compared to the total output width

kIntelVvpScalerParameterErr, if the split_input_width value computed during the call is larger than allowed by the configuration. Note that this value is computed last and the scaler is still reprogrammed in this case.

intel_vvp_scaler_set_split_v_scaling

Prototype 
int intel_vvp_scaler_set_split_v_scaling(intel_vvp_scaler_instance *instance, uint32_t total_input_height, uint32_t total_output_height, uint32_t split_output_height, uint32_t split_output_top_offset, bool extended_fill, uint32_t *split_input_height, uint32_t *split_input_top_offset);
Description

Description This function sets the scaler for split vertical scaling. Specify the full height of the input image, the full height of the desired output image and the required offset/height of the output split to set up the scaler to generate the given output band. Optionally, the function returns the offset and height of the corresponding band in the input image. This should be used to configure the upstream video processing pipeline and stream the correct video portion into the scaler. This call does not update the input height image info register in Lite mode. intel_vvp_core_set_img_info_height should still be called, presumably using the split_input_height value returned here as a parameter.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

total_input_height – new height of the full input image

total_output_height – new height of the full output image

split_output_height – height of the scaled split (at the output)

split_output_top_offset – top offset of the scaled split (at the output)

extended_fill – if the input split should contain extra lines on the top and/or bottom to ensure the output splits can be stitched with a joint that is not noticeable

split_input_height – the recommended height for the input split. The value is computed and returned by this call (optional, may be NULL)

split_input_top_offset – the recommended top offset for the input split respective to the full input image. The value is computed and returned by this call (optional, may be NULL)

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or not configured for split vertical scaling

kIntelVvpScalerParameterErr, if one of the dimensions is invalid

kIntelVvpScalerParameterErr, if the height and top offset of the output split go out-of-range compared to the total output height

intel_vvp_scaler_set_v_bank

Prototype 
 int intel_vvp_scaler_set_v_bank(intel_vvp_scaler_instance *instance, uint8_t bank);
Description

Selects the bank of vertical scaler coefficient to use. The instance must be a valid intel_vvp_scaler_instance, fully initialized, and configured for vertical polyphase scaling. Also, the bank of vertical coefficient should be valid

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

bank – the identifier for the horizontal bank in the range [0..num_v_banks-1] where v_num_banks is the value returned by intel_vvp_scaler_get_num_vertical_banks

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or not configured for vertical polyphase scaling

kIntelVvpScalerParameterErr if the vertical bank is invalid

intel_vvp_scaler_set_h_bank

Prototype 
 int intel_vvp_scaler_set_h_bank(intel_vvp_scaler_instance *instance, uint8_t bank);
Description

Selects the bank of horizontal scaler coefficient to use. The instance must be a valid intel_vvp_scaler_instance, fully initialized, and configured for horizontal polyphase scaling. Also, the bank of horizontal coefficient should be valid

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

bank – the identifier for the horizontal bank in the range [0..num_h_banks-1] where h_num_banks is the value returned by intel_vvp_scaler_get_num_horizontal_banks

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or not configured for horizontal polyphase scaling

kIntelVvpScalerParameterErr if the horizontal bank is invalid

intel_vvp_scaler_get_output_width

Prototype 
 uint32_t intel_vvp_scaler_get_output_width(intel_vvp_scaler_instance *instance)
Description

Returns the selected output width. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for horizontal scaling. Also, debug should be enabled to read a sensible value back

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

the selected output width

intel_vvp_scaler_get_total_input_width

Prototype 
uint32_t intel_vvp_scaler_get_total_input_width(intel_vvp_scaler_instance *instance)
Description

Returns the selected total input width. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split horizontal scaling. Also, debug should be enabled to read a sensible value back

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

the selected total input width for the full image

intel_vvp_scaler_get_total_output_width

Prototype 
uint32_t intel_vvp_scaler_get_total_output_width(intel_vvp_scaler_instance *instance)
Description

Returns the selected total output width. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split horizontal scaling. Also, debug should be enabled to read a sensible value back

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

the selected total output width for the full image

intel_vvp_scaler_get_output_height

Prototype 
 uint32_t intel_vvp_scaler_get_output_height(intel_vvp_scaler_instance *instance)
Description

Returns the selected output height. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for vertical scaling. Also, debug should be enabled to read a sensible value back

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

the selected output height

intel_vvp_scaler_get_total_input_height

Prototype 
uint32_t intel_vvp_scaler_get_total_input_height(intel_vvp_scaler_instance *instance)
Description

Returns the selected total input height. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split vertical scaling. Also, debug should be enabled to read a sensible value back

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

the selected total input height for the full image

intel_vvp_scaler_get_total_output_height

Prototype 
uint32_t intel_vvp_scaler_get_total_output_height (intel_vvp_scaler_instance *instance)
Description

Returns the selected total output height. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split vertical scaling. Also, debug should be enabled to read a sensible value back

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

the selected total output height for the full image

intel_vvp_scaler_get_h_pos_error

Prototype 
uint32_t intel_vvp_scaler_get_h_pos_error(intel_vvp_scaler_instance *instance)
Description

Returns the selected horizontal position error. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split horizontal scaling. Also, debug should be enabled to read a sensible value back

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

the selected horizontal position error for the full image

intel_vvp_scaler_get_v_pos_error

Prototype 
uint32_t intel_vvp_scaler_get_v_pos_error(intel_vvp_scaler_instance *instance)
Description

Returns the selected vertical position error. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split vertical scaling. Also, debug should be enabled to read a sensible value back

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

the selected vertical position error for the full image

intel_vvp_scaler_get_h_extended_fill

Prototype 
bool intel_vvp_scaler_get_h_extended_fill(intel_vvp_scaler_instance *instance)
Description

Returns if horizontal extended fill is enabled. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split horizontal scaling. Also, debug should be enabled to read a sensible value back

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

if horizontal extended fill is assumed

intel_vvp_scaler_get_v_extended_fill

Prototype 
bool intel_vvp_scaler_get_v_extended_fill(intel_vvp_scaler_instance *instance)
Description

Returns if vertical extended fill is enabled. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split vertical scaling. Also, debug should be enabled to read a sensible value back

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

if vertical extended fill is assumed

intel_vvp_scaler_get_h_phase_offset_error

Prototype 
int intel_vvp_scaler_get_h_phase_offset_error(intel_vvp_scaler_instance *instance, uint32_t *phase_offset, uint32_t *phase_error)
Description

Returns the selected horizontal phase offset and phase offset error. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split horizontal polyphase scaling. Also, debug should be enabled to read sensible values back

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

kIntelVvpCoreOk in case of success, negative error code otherwise

kIntelVvpCoreInstanceErr if the instance is invalid, or not configured for horizontal split scaling with polyphase scaling algorithm

kIntelVvpCoreNullPtrErr if phase_offset or phase_error are NULL pointers

intel_vvp_scaler_get_ v_phase_offset_error

Prototype 
int intel_vvp_scaler_get_v_phase_offset_error(intel_vvp_scaler_instance *instance, uint32_t *phase_offset, uint32_t *phase_error)
Description

Returns the selected vertical phase offset and phase offset error. The instance must be a valid intel_vvp_scaler_instance fully initialized and configured for split horizontal polyphase scaling. Also, debug should be enabled to read a sensible value back

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

kIntelVvpCoreOk in case of success, negative error code otherwise

kIntelVvpCoreInstanceErr if the instance is invalid, or not configured for vertical split scaling with polyphase scaling algorithm

kIntelVvpCoreNullPtrErr if phase_offset or phase_error are NULL pointers

intel_vvp_scaler_get_v_bank

Prototype 
 uint8_t intel_vvp_scaler_get_v_bank(intel_vvp_scaler_instance *instance);
Description

Returns the selected bank of vertical scaling coefficient. The instance must be a valid intel_vvp_scaler_instance, fully initialized, and configured for vertical polyphase scaling. Also, debug must be enabled to read a sensible value back.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

the selected vertical bank

intel_vvp_scaler_get_h_bank

Prototype 
 uint8_t intel_vvp_scaler_get_h_bank(intel_vvp_scaler_instance *instance);
Description

Returns the selected bank of horizontal scaling coefficient. The instance must be a valid intel_vvp_scaler_instance, fully initialized, and configured for horizontal polyphase scaling. Also, debug must be enabled to read a sensible value back.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

the selected horizontal bank

intel_vvp_scaler_set_quantized_coeffs

Prototype 
 int intel_vvp_scaler_set_quantized_coeffs(intel_vvp_scaler_instance* instance, bool h_coeffs, const int32_t* quantized_coeffs, uint8_t num_coeffs, uint8_t bank, uint8_t phase);
Description

Programs the IP with a new set of num_coeffs coefficients for the specified horizontal or vertical phase in the specified bank of coefficients. An error is returned if the IP is not properly configured to use these coefficients. The num_coeffs parameter indicates the guaranteed minimum size of the quantized_coeffs array and must match with the number of horizontal or vertical taps as appropriate. Also, the call checks for correctness of the quantized values and returns an error if invalid bits are set. Sign extension to the full 32 bit range is accepted. Quantization errors do not prevent the coefficients from being updated

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

h_coeffs – true if committing a set of horizontal coefficients, false for a set of vertical coefficients

quantized_coeffs – pointer to the structure containing the quantized coefficients

num_coeffs – the number of horizontal taps if h_coeffs is true, otherwise the number of vertical taps. The caller guarantees that the quantized_coeffs array is larger than the specified number of values

bank – the bank of coefficients used to commit the new set

phase – the phase for the set of new coefficients

Returns

kIntelVvpCoreOk in case of success, negative error code otherwise

kIntelVvpCoreInstanceErr if the instance is invalid, or not configured for horizontal/vertical polyphase scaling and run-time loading of coefficients

kIntelVvpScalerParameterErr if the phase, bank or number of coefficients are invalid for the IP configuration

kIntelVvpCoreNullPtrErr if quantized_coeffs is a NULL pointer

kIntelVvpScalerQuantizationErr if the quantized coefficients are out-of-range (this does not prevent the coefficients update)

intel_vvp_scaler_set_coeffs

Prototype 
 int intel_vvp_scaler_set_coeffs(intel_vvp_scaler_instance* instance, bool h_coeffs, const float* quantized_coeffs, uint8_t num_coeffs, uint8_t bank, uint8_t phase);
Description

Programs the IP with a new set of num_coeffs coefficients for the specified horizontal or vertical phase in the specified bank of coefficients. Coefficients are quantized using the fixed-point configuration reported by the IP. An error is returned if the IP is not properly configured to use these coefficients. The num_coeffs parameter indicates the guaranteed minimum size of the coeffs array and must match with the number of horizontal or vertical taps as appropriate. An error is returned if the quantization could not be achieved successfully.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

h_coeffs – true if committing a set of horizontal coefficients, false for a set of vertical coefficients

coeffs – pointer to the structure containing the set of floating-point coefficients

num_coeffs – the number of horizontal taps if h_coeffs is true, otherwise the number of vertical taps. The caller guarantees that the quantized_coeffs array is larger than the specified number of values

bank – the bank of coefficients used to commit the new set

phase – the phase for the set of new coefficients

Returns

kIntelVvpCoreOk in case of success, negative error code otherwise

kIntelVvpCoreInstanceErr if the instance is invalid, or not configured for horizontal/vertical polyphase scaling and run-time loading of coefficients

kIntelVvpScalerParameterErr if the phase, bank or number of coefficients are invalid for the IP configuration

kIntelVvpCoreNullPtrErr if quantized_coeffs is a NULL pointer

kIntelVvpScalerQuantizationErr if the quantized coefficients are out-of-range for the quantization constraints (which does not prevent the coefficients update)

intel_vvp_scaler_commit_writes

Prototype 
 int intel_vvp_scaler_commit_writes(intel_vvp_scaler_instance* instance)
Description

Commits all pending writes before processing the next field. The instance must be valid and parameterized in full mode.

Arguments

instance – pointer to the intel_vvp_scaler_instance software driver instance structure

Returns

kIntelVvpCoreOk (0) for success, negative error code otherwise

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