5.7. Source Interfaces

Table 20. Controller Interface
Interface	Port Type	Clock Domain	Port	Direction	Description
clk	Clock	N/A	`clk`	Input	Clock for embedded controller
reset	Reset	`clk`	`reset`	Input	Reset for embedded controller
tx_mgmt	AV-MM	`clk`	`tx_mgmt_address[8:0]`	Input	32-bit word addressing address
			`tx_mgmt_chipselect`	Input	Assert for valid read or write access
			`tx_mgmt_read`	Input	Assert to indicate a read transfer
			`tx_mgmt_write`	Input	Assert to indicate a write transfer
			`tx_mgmt_writedata[31:0]`	Input	Data for write transfers
			`tx_mgmt_readdata[31:0]`	Output	Data for read transfers
			`tx_mgmt_waitrequest`	Output	Asserted when the DisplayPort Intel® FPGA IP is unable to respond to a read or write request. Forces the GPU to wait until the IP is ready to proceed with the transfer.
tx_mgmt_irq	IRQ	`clk`	`tx_mgmt_irq`	Output	Interrupt for embedded controller

Table 21. Transceiver Management Interface `n` is the number of TX lanes.
Interface	Port Type	Clock Domain	Port	Direction	Description
xcvr_mgmt_clk	Clock	N/A	`xcvr_mgmt_clk`	Input	Transceiver management clock
clk_cal	Clock	N/A	`clk_cal`	Input	A 50-MHz calibration clock input. This clock must be synchronous to the clock used for the Transceiver Reconfiguration block (`xvcr_mgmt_clk`), external to the DisplayPort source.
tx_analog_reconfig	Conduit	`xcvr_mgmt_clk`	`tx_vod[2n - 1:0]`	Output	Transceiver analog reconfiguration handshaking
			`tx_emp[2n - 1:0]`	Output
			`tx_analog_reconfig_req`	Output
			`tx_analog_reconfig_ack`	Input
			`tx_analog_reconfig_busy`	Input
tx_reconfig	Conduit	`xcvr_mgmt_clk`	`tx_link_rate[1:0]`	Output	Transceiver link rate reconfiguration handshaking
			`tx_link_rate_8bits[7:0]`	Output
			`tx_reconfig_req`	Input
			`tx_reconfig_ack`	Input
			`tx_reconfig_busy`	Input

Note: Value of tx_link_rate[1:0]: 0 = 1.62 Gbps, 1 = 2.70 Gbps, 2 = 5.40 Gbps, 3 = 8.10 Gbps; value of tx_link_rate_8bits[7:0]: 0x06 = 1.62 Gbps, 0x0a = 2.70 Gbps, 0x14 = 5.40 Gbps, 0x1e = 8.10 Gbps.

Note: For devices using a 50-MHz xcvr_mgmt_clk clock, connect the same clock directly also to the clk_cal signal. For devices using a 100-MHz xcvr_mgmt_clk clock, connect the same clock to clk_cal signal through a by-2 divider.

Transceiver Analog Reconfiguration Interface

Transceiver Reconfiguration Interface

Video Interface

When you turn off Enable Video input Image port, the source uses the standard HSYNC/VSYNC/DE ports in txN_vid_clk and txN_video_in interfaces.

Table 22. Video Interface (HSYNC/VSYNC/DE Interface) `v` is the number of bits per color, p is the pixels per clock (1 = single, 2 = dual, and 4 = quad). `N` is the stream number; for example, `tx_vid_clk` represents Stream 0, `tx1_vid_clk` represents Stream 1, and so on.
Interface	Port Type	Clock Domain	Port	Direction	Description
txN_vid_clk	Clock	N/A	`txN_vid_clk`	Input	Video clock
txN_video_in	Conduit	`txN_vid_clk`	`txN_vid_data[3v*p-1:0]`	Input	Video data and standard H/V synchronization video port input
			`txN_vid_v_sync[p-1:0]`	Input
			`txN_vid_h_sync[p-1:0]`	Input
			`txN_vid_de[p-1:0]`	Input

When you turn on Enable Video input Image port, the source uses the txN_im_clk and txN_video_in_im interfaces.

Table 23. Video Interface (TX Video IM Interface) `v` is the number of bits per color, p is the pixels per clock (1 = single, 2 = dual, and 4 = quad). `N` is the stream number; for example, `tx_im_clk` represents Stream 0, `tx1_im_clk` represents Stream 1, and so on.
Interface	Port Type	Clock Domain	Port	Direction	Description
txN_im_clk	Clock	N/A	`txN_im_clk`	Input	Video Image clock
txN_video_in	Conduit	`txN_im_clk`	`txN_im_sol`	Input	Start of video line
			`txN_im_eol`	Input	End of video line
			`txN_im_sof`	Input	Start of video frame
			`txN_im_eof`	Input	End of video frame
			`txN_im_data[3v*p-1:0]`	Input	Video input data
			`txN_im_valid[p-1:0]`	Input	Video data valid. Each bit must assert when all other signals on this port are valid and the corresponding pixel belongs to active video.
			`txN_im_locked`	Input	Video locked 0 = Unlocked 1 = Locked
			`txN_im_interlace`	Input	Video interlaced 0 = Progressive video 1 = Interlaced video
			`txN_im_field`	Input	Video field 0 = Bottom field (or progressive) 1 = Top field

Table 24. AUX Interface
Interface	Port Type	Clock Domain	Port	Direction	Description
aux_clk	Clock	N/A	`aux_clk`	Input	AUX channel clock
aux_reset	Reset	`aux_clk`	`aux_reset`	Input	Active-high AUX channel reset
tx_aux	Conduit	`aux_clk`	`tx_aux_in`	Input	AUX channel data input
			`tx_aux_out`	Output	AUX channel data output
			`tx_aux_oe`	Output	Output buffer enable
			`tx_hpd`	Input	Hot plug detect
tx_aux_debug	AV-ST	`aux_clk`	`tx_aux_debug_data[31:0]`	Output	Formatted AUX channel debug data
			`tx_aux_debug_valid`	Output	Asserted when all the other signals on this port are valid
			`tx_aux_debug_sop`	Output	Start of packet (start of AUX request or reply)
			`tx_aux_debug_eop`	Output	End of packet (end of AUX request or reply)
			`tx_aux_debug_err`	Output	Asserted when an AUX channel bit error is detected
			`tx_aux_debug_cha`	Output	The channel number for data being transferred on the current cycle. Used as AUX channel data direction. 0 = Reply (from DisplayPort sink) 1 = Request (to DisplayPort sink)

AUX Interface

Table 25. Secondary Interface `N` is the stream number; for example, `tx_ss` represents Stream 0, `tx1_ss` represents Stream 1, and so on.
Interface	Signal Type	Clock Domain	Port	Direction	Description
tx_ss_clk	Clock	N/A	`tx_ss_clk`	Output	TX transceiver clock out and clock for secondary stream
Secondary Stream (txN_ss)	AV-ST	`tx_ss_clk`	`txN_ss_data[127:0]`	Input	Secondary stream interface
			`txN_ss_valid`	Input
			`txN_ss_ready`	Output
			`txN_ss_sop`	Input
			`txN_ss_eop`	Input

Secondary Stream Interface

Table 26. Audio Interface `m` is the number of TX audio channels. `N` is the stream number; for example, `tx_audio` represents Stream 0, `tx1_audio` represents Stream 1, and so on.
Interface	Signal Type	Clock Domain	Port	Direction	Description
Audio (txN_audio)	Clock	N/A	`txN_audio_clk`	Input	Audio clock
	Conduit	`txN_audio_clk`	`txN_audio_lpcm_data [m*32-1:0]`	Input	m channels of 32-bit audio sample data.
			`txN_audio_valid`	Input	Must be asserted when valid data is available on `txN_audio_lpcm_data`
			`txN_audio_mute`	Input	Must be asserted when audio is muted

Audio Interface

Table 27. TX Transceiver Interface `n` is the number of TX lanes, `s` is the number of symbols per clock.
Note: Connect the DisplayPort signals to the Native PHY signals of the same name.
Interface	Port Type	Clock Domain	Port	Direction	Description
TX transceiver interface	Clock	N/A	`tx_std_clkout[n–1:0]`	Input	TX transceiver clock out. Equivalent to Link Speed Clock (`ls_clk`).
	Conduit	`tx_std_clkout`	`tx_parallel_data[ns10–1:0]`	Output	Parallel data for TX transceiver
	Conduit	N/A	`tx_pll_powerdown`	Output	PLL power down for TX transceiver
	Conduit	`xcvr_mgmt_clk`	`tx_digitalreset[n–1:0]`	Output	Resets the digital TX portion of TX transceiver Note: Required only for Arria V, Cyclone V, and Stratix V devices.
	Conduit	N/A	`tx_analogreset[n–1:0]`	Output	Resets the analog TX portion of TX transceiver Note: Required only for Arria V, Cyclone V, and Stratix V devices.
	Conduit	N/A	`tx_cal_busy[n–1:0]`	Input	Calibration in progress signal from TX transceiver
	Conduit	N/A	`tx_pll_locked`	Input	PLL locked signal from TX transceiver

Table 28. HDCP InterfaceApplicable only when you turn on the Support HDCP 2.3 or Support HDCP 1.3 parameters.
Interface	Port Type	Clock Domain	Port	Direction	Description
HDCP Clocks (`hdcp_clks`)	Reset	–	`hdcp_reset`	Input	Main asynchronous reset for HDCP.
	Clock	–	`csr_clk`	Input	HDCP clock for control and status registers. Typically, shares the Nios II processor clock (100 MHz).
	Clock	–	`crypto_clk`	Input	HDCP 2.3 clock for authentication and cryptographic layer. You can use any clock with a frequency of up to 200 MHz. Not applicable for HDCP 1.3. Note: The clock frequency determines the authentication latency.
CSR Interface (`tx_csr`)	Avalon-MM	`csr_clk`	`tx_csr_addr[7:0]`	Input	The Avalon-MM slave port that provides access to internal control and status register, mainly for authentication messages transfer. This interface is expected to operate at Nios II processor clock domain. Because of the extremely large bit portion of message, the IP transfers the message in burst mode with full handshaking mechanism. Write transfers always have a wait time of 0 cycle while read transfers have a wait time of 1 cycle. The addressing should be accessed as word addressing in the Platform Designer flow. For example, addressing of 4 in the Nios II software selects the address of 1 in the slave.
			`tx_csr_wr`	Input
			`tx_csr_rd`	Input
			`tx_csr_wrdata[31:0]`	Input
			`tx_csr_rddata[31:0]`	Output
HDCP Key and Status Interface (`tx_hdcp`)	Conduit (Key)	`crypto_clk`	`tx_kmem_wait[0]` (HDCP 2.3) `tx_kmem_wait[1]` (HDCP 1.3)	Input	Always keep this signal asserted until the key is ready to be read. This signal is not available if you turn on the Support HDCP Key Management parameter.
			`tx_kmem_rdaddr[3:0]` (HDCP 2.3) `tx_kmem_rdaddr[9:4]` (HDCP 1.3)	Output	Key read address bus. [3:2] = Reserved. This signal is not available if you turn on the Support HDCP Key Management parameter.
			`tx_kmem_q[31:0]` (HDCP 2.3) `tx_kmem_q[87:32]` (HDCP 1.3)	Input	Key data for read transfers. Read transfer always have a wait time of 1 cycle. This signal is not available if you turn on the Support HDCP Key Management parameter.
	Avalon-MM	`csr_clk`	`tx_hdcp1_kmem_wr`	Input	The Avalon® memory-mapped slave port provides write access to internal HDCP 1.3 key storage. Write transfers always have a wait time of 0. The Avalon® memory-mapped master access the addressing as word addressing in the Platform Designer flow. For example, addressing of 4 in the Avalon® memory-mapped master selects the address of 1 in the slave. These signals are only available if you turn on the Support HDCP Key Management parameter and the Support HDCP 1.3 parameter.
			`tx_hdcp1_kmem_wrdata[31:0]`	Input
			`tx_hdcp1_kmem_addr[6:0]`	Input
	Avalon-MM	`csr_clk`	`tx_hdcp2_kmem_wr`	Input	The Avalon® memory-mapped slave port provides write access to internal HDCP 2.3 key storage. Write transfers always have a wait time of 0. The Avalon® memory-mapped master access the addressing as word addressing in the Platform Designer flow. For example, addressing of 4 in the Avalon® memory-mapped master selects the address of 1 in the slave. These signals are only available if you turn on the Support HDCP Key Management parameter and the Support HDCP 2.3 parameter.
			`tx_hdcp2_kmem_wrdata[31:0]`	Input
			`tx_hdcp2_kmem_addr[3:0]`	Input
	Conduit	`tx_std_clkout[0]`	`tx_hdcp1_enabled`	Output	This signal is asserted by the IP if the outgoing video and secondary data are HDCP 1.3 encrypted.
		`tx_std_clkout[0]`	`tx_hdcp2_enabled`	Output	This signal is asserted by the IP if the outgoing video and secondary data are HDCP 2.3 encrypted.
		`csr_clk`	`tx_hdcp1_disable`	Input	Assert this signal to disable the HDCP 1.3 IP. Note: You must reset the HDCP IP (`hdcp_reset`) after toggling this signal. You must not call the software API `hdcp_main()` while this signal is asserted. You must call the software API `hdcp_unauth()` after deasserting this signal.
		`csr_clk`	`tx_hdcp2_disable`	Input	Assert this signal to disable the HDCP 2.3 IP. Note: You must reset the HDCP IP (`hdcp_reset`) after toggling this signal. You must not call the software API `hdcp_main()` while this signal is asserted. You must call the software API `hdcp_unauth()` after deasserting this signal.

Transceiver Reconfiguration Interface

Select Your Language

Using Intel.com Search

Quick Links

Recent Searches

Advanced Search

Only search in

DisplayPort Intel® FPGA IP User Guide

5.7. Source Interfaces

Video Interface