DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 11/12/2021
Public

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Document Table of Contents

1.1. DisplayPort Terms and Acronyms

The tables list the commonly used DisplayPort terms and acronyms.
Table 1.  DisplayPort Acronyms
Acronym Description
API Application Programming Interface
AUX Auxiliary
bpc Bits per Component
bpp Bits per Pixel
BE Blanking End
BS Blanking Start
DP DisplayPort
DPCD DisplayPort Configuration Data
eDP Embedded DisplayPort
EDID Enhanced Display Identification Data
GPU Graphics Processor Unit
HBR High Bit Rate (2.7 Gbps per lane)
HBR2 High Bit Rate 2 (5.4 Gbps per lane)
HBR3 High Bit Rate 3 (8.1 Gbps per lane)
HPD Hot Plug Detect
MST Multi-Stream Transport
Maud M value for audio
Mvid M value for video
Naud N value for audio
Nvid N value for video
RBR Reduced Bit Rate (1.62 Gbps per lane)
RGB Red Green Blue
RX Receiver
SDP Secondary-Data Packet
SE SDP End
SR Scrambler Reset
SS SDP Start
SST Single-Stream Transport
TX Transmitter
Table 2.  DisplayPort Terms
Term Definition
Link Symbol Clock (LSym_Clk) Link Symbol clock frequency (f_LSym_Clk) across link rate: -
  • HBR3 (8.1Gbps) = 810 MHz
  • HBR2 (5.4Gbps) = 540 MHz
  • HBR (2.7Gbps) = 270 MHz
  • RBR (1.62Gbps) = 162 MHz
Note: LSym_Clk is equivalent to LS_Clk in VESA DisplayPort Standard version 1.4.
Link Speed Clock (ls_clk)

Transceiver recovered clock out.

Link Speed clock frequency equals:

f_LSym_Clk / SYMBOLS_PER_CLOCK.

Stream Clock or Pixel Clock (Strm_Clk)

Used for transferring stream data into a DisplayPort transmitter within a DisplayPort Source device or from a DisplayPort receiver within a DP Sink device. Video and audio (optional) are likely to have separate stream clocks.

Stream clock frequency (f_Strm_Clk) represent the pixel rate. For example, f_Strm_Clk for 1080p60 (CEA-861-F VIC16) is 148.5 Mhz.

Video Clock (vid_clk)

Video clock frequency equals:

f_Strm_Clk / PIXELS_PER_CLOCK