Early Power Estimator User Guide

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ID 683272
Date 7/16/2021
Public
Document Table of Contents
Document Table of Contents x
1. Early Power Estimator Overview 2. Setting Up the Early Power Estimator 3. Early Power Estimator Worksheets 4. Factors Affecting the Early Power Estimator Spreadsheet Accuracy A. Additional Information for Early Power Estimator User Guide
1. Early Power Estimator Overview x
1.1. Release Information 1.2. Power Model Status for Supported Device Families
2. Setting Up the Early Power Estimator x
2.1. System Requirements 2.2. Download and Install the Early Power Estimator 2.3. Estimating Power Consumption
2.2. Download and Install the Early Power Estimator x
2.2.1. Changing the Macro Security Level in Microsoft Excel 2003 2.2.2. Changing the Macro Security Level in Microsoft Excel 2007 2.2.3. Changing the Macro Security Level in Microsoft Excel 2010
2.3. Estimating Power Consumption x
2.3.1. Estimating Power Consumption Before Starting the FPGA Design 2.3.2. Estimating Power Consumption While Creating the FPGA Design 2.3.3. Estimating Power Consumption After Completing the FPGA Design
2.3.1. Estimating Power Consumption Before Starting the FPGA Design x
2.3.1.1. Entering Information into the Early Power Estimator
2.3.1.1. Entering Information into the Early Power Estimator x
2.3.1.1.1. Manually Entering Values
2.3.2. Estimating Power Consumption While Creating the FPGA Design x
2.3.2.1. Importing a File
2.3.2.1. Importing a File x
2.3.2.1.1. Generate the EPE File 2.3.2.1.2. Import Data into the EPE Spreadsheet
3. Early Power Estimator Worksheets x
3.1. Main Worksheet 3.2. Logic Worksheet 3.3. RAM Worksheet 3.4. DSP Worksheet 3.5. I/O Worksheet 3.6. PLL Worksheet 3.7. Clock Worksheet 3.8. HSDI Worksheet 3.9. XCVR Worksheet 3.10. HMC Worksheet 3.11. IP Worksheet 3.12. HPS Worksheet 3.13. Report Worksheet 3.14. Enpirion Worksheet
3.1. Main Worksheet x
3.1.1. Input Parameter 3.1.2. Thermal Power 3.1.3. Power Tree Design 3.1.4. Thermal Analysis
3.1.4. Thermal Analysis x
3.1.4.1. Not Using a Heat Sink 3.1.4.2. Using a Heat Sink
3.13. Report Worksheet x
3.13.1. Static Power and Dynamic Current per Voltage Rail 3.13.2. Power Up Current 3.13.3. Power Breakout for Multiple Voltage Supplies 3.13.4. Power Regulator Settings
4. Factors Affecting the Early Power Estimator Spreadsheet Accuracy x
4.1. Toggle Rate 4.2. Airflow 4.3. Temperature 4.4. Heat Sink
A. Additional Information for Early Power Estimator User Guide x
A.1. Document Revision History for Early Power Estimator User Guide
1. Early Power Estimator Overview
2. Setting Up the Early Power Estimator
3. Early Power Estimator Worksheets
4. Factors Affecting the Early Power Estimator Spreadsheet Accuracy
A. Additional Information for Early Power Estimator User Guide

3.7. Clock Worksheet

Intel FPGA devices support global, regional, or periphery clock networks. The EPE spreadsheet does not distinguish between global or regional clocks because the difference in power is not significant.

Each row in the Clock worksheet of the EPE spreadsheet represents a clock network or a separate clock domain. Enter the following parameters for each design module:

  • Clock frequency (in MHz)
  • Total fanout for each clock network used
  • Global clock enable percentage
  • Local clock enable percentage
Figure 21. Clock Worksheet of the EPE Spreadsheet
Table 13.  Clock Worksheet Information
Column Heading Description
Domain Specify a name for the clock network in this column. This is an optional value.
Clock Freq (MHz) Enter the frequency of the clock domain. This value is limited by the maximum frequency specification for the device family.
Total Fanout Enter the total number of flipflops and RAM, DSP, and I/O blocks fed by this clock. The number of resources driven by every global clock and regional clock signal is reported in the Fan-out column of the Quartus II Compilation Report. In the Compilation Report, select Fitter and click Resources Section. Select Global and Other Fast Signals and click Fan-out.
Global Enable % Enter the average percentage of time that the entire clock tree is enabled. Each global clock buffer has an enable signal that you can use to dynamically shut down the entire clock tree.
Local Enable %

Enter the average percentage of time that clock enable is high for destination flipflops.

Local clock enables for flipflops in ALMs are promoted to LAB-wide signals. When a given flipflop is disabled, the LAB-wide is clock disabled, cutting clock power and the power for down-stream logic. This worksheet models only the impact on clock tree power.

Total Power (W) This is the total power dissipation due to clock distribution (in watts). This value is automatically calculated.
User Comments Enter any comments. This is an optional entry.

For more information about the clock networks of the supported device families, refer to the “Clock Networks and PLLs” chapter of the respective device handbook.

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