P-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express 2. IP Architecture and Functional Description 3. Parameters 4. Interfaces 5. Advanced Features 6. Troubleshooting/Debugging 7. Document Revision History for the P-tile Avalon® Memory-mapped Intel FPGA IP for PCI Express User Guide A. Configuration Space Registers
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express x
1.1. Overview 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Performance and Resource Utilization 1.6. IP Core and Design Example Support Levels
2. IP Architecture and Functional Description x
2.1. Top-Level Architecture 2.2. Functional Description
2.1. Top-Level Architecture x
2.1.1. Avalon® -MM Bridge Architecture 2.1.2. Clock Domains 2.1.3. Refclk 2.1.4. Reset
2.2. Functional Description x
2.2.1. PMA/PCS 2.2.2. Data Link Layer Overview 2.2.3. Transaction Layer Overview 2.2.4. Avalon® -MM Bridge
2.2.4. Avalon® -MM Bridge x
2.2.4.1. Endpoint Mode with Data Movers 2.2.4.2. Endpoint Mode 2.2.4.3. Root Port Mode
3. Parameters x
3.1. Top-Level Settings 3.2. Core Parameters 3.3. Avalon-MM Settings
3.2. Core Parameters x
3.2.1. Base Address Registers 3.2.2. PCI Express and PCI Capabilities Parameters 3.2.3. Device Identification Registers 3.2.4. Configuration, Debug and Extension Options
3.2.2. PCI Express and PCI Capabilities Parameters x
3.2.2.1. Device Capabilities 3.2.2.2. Link Capabilities 3.2.2.3. Legacy Interrupt Pin Register 3.2.2.4. MSI Capabilities 3.2.2.5. MSI-X Capabilities 3.2.2.6. Device Serial Number Capability 3.2.2.7. TLP Processing Hints (TPH)
4. Interfaces x
4.1. Overview 4.2. Clocks and Resets 4.3. Avalon® -MM Interface 4.4. Serial Data Interface 4.5. Hard IP Status Interface 4.6. Interrupt Interface 4.7. Hot Plug Interface (RP Only) 4.8. Power Management Interface 4.9. Configuration Output Interface 4.10. Hard IP Reconfiguration Interface 4.11. PHY Reconfiguration Interface
4.2. Clocks and Resets x
4.2.1. Interface Clock Signals 4.2.2. Interface Reset Signals
4.3. Avalon® -MM Interface x
4.3.1. Endpoint Mode Interface (512-bit Avalon® -MM Interface) 4.3.2. Root Port Mode Interface (256-bit Avalon® -MM Interface)
4.3.1. Endpoint Mode Interface (512-bit Avalon® -MM Interface) x
4.3.1.1. Bursting Avalon® -MM Master and Conduit 4.3.1.2. Bursting Avalon® -MM Slave and Conduit 4.3.1.3. Read Data Mover 4.3.1.4. Write Data Mover 4.3.1.5. Descriptor Format for Data Movers 4.3.1.6. Avalon® -MM DMA Operations
4.3.1.1. Bursting Avalon® -MM Master and Conduit x
4.3.1.1.1. Bursting Avalon® -MM Master and Conduit in Non-Bursting Mode
4.3.1.2. Bursting Avalon® -MM Slave and Conduit x
4.3.1.2.1. Bursting Avalon® -MM Slave and Conduit in Non-Bursting Mode
4.3.1.3. Read Data Mover x
4.3.1.3.1. Read Data Mover Avalon® -MM Write Master and Conduit 4.3.1.3.2. Read Data Mover Avalon® -ST Descriptor Sinks 4.3.1.3.3. Read Data Mover Status Avalon® -ST Source
4.3.1.4. Write Data Mover x
4.3.1.4.1. Write Data Mover Avalon® -MM Read Master and Conduit 4.3.1.4.2. Write Data Mover Avalon® -ST Descriptor Sinks 4.3.1.4.3. Write Data Mover Status Avalon® -ST Source
4.3.2. Root Port Mode Interface (256-bit Avalon® -MM Interface) x
4.3.2.1. High Performance Avalon® -MM Slave (HPTXS) Interface 4.3.2.2. High Performance Avalon® -MM Master (HPRXM) Interface 4.3.2.3. 32-Bit Control Register Access (CRA) Slave (Root Port only)
4.6. Interrupt Interface x
4.6.1. Legacy Interrupts 4.6.2. MSI 4.6.3. MSI-X
4.6.3. MSI-X x
4.6.3.1. Implementing MSI-X Interrupts
4.10. Hard IP Reconfiguration Interface x
4.10.1. Address Map for the User Avalon-MM Interface 4.10.2. Configuration Registers Access
4.10.2. Configuration Registers Access x
4.10.2.1. Using Direct User Avalon-MM Interface (Byte Access) 4.10.2.2. Using the Debug Register Interface Access
5. Advanced Features x
5.1. PCIe* Port Bifurcation and PHY Channel Mapping
6. Troubleshooting/Debugging x
6.1. Hardware 6.2. Debug Toolkit
6.1. Hardware x
6.1.1. Debugging Link Training Issues 6.1.2. Debugging Data Transfer and Performance Issues
6.1.1. Debugging Link Training Issues x
6.1.1.1. Generic Tools and Utilities 6.1.1.2. SignalTapII Logic Analyzer 6.1.1.3. Additional Debug Tools
6.1.2. Debugging Data Transfer and Performance Issues x
6.1.2.1. Advanced Error Reporting (AER) 6.1.2.2. Second-Level Debug Tools
6.2. Debug Toolkit x
6.2.1. Overview 6.2.2. Enabling the P-Tile Debug Toolkit 6.2.3. Launching the P-Tile Debug Toolkit 6.2.4. Using the P-Tile Debug Toolkit 6.2.5. Enabling the P-Tile Link Inspector 6.2.6. Using the P-Tile Link Inspector
A. Configuration Space Registers x
A.1. Configuration Space Registers A.2. Intel-Defined VSEC Capability Registers
A.1. Configuration Space Registers x
A.1.1. Register Access Definitions A.1.2. PCIe Configuration Header Registers A.1.3. PCI Express Capability Structures A.1.4. Physical Layer 16.0 GT/s Extended Capability Structure A.1.5. MSI-X Registers
A.2. Intel-Defined VSEC Capability Registers x
A.2.1. Intel-Defined VSEC Capability Header (Offset 00h) A.2.2. Intel-Defined Vendor Specific Header (Offset 04h) A.2.3. Intel Marker (Offset 08h) A.2.4. JTAG Silicon ID (Offset 0x0C - 0x18) A.2.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D) A.2.6. General Purpose Control and Status Register (Offset 0x30) A.2.7. Uncorrectable Internal Error Status Register (Offset 0x34) A.2.8. Uncorrectable Internal Error Mask Register (Offset 0x38) A.2.9. Correctable Internal Error Status Register (Offset 0x3C) A.2.10. Correctable Internal Error Mask Register (Offset 0x40)
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express
2. IP Architecture and Functional Description
3. Parameters
4. Interfaces
5. Advanced Features
6. Troubleshooting/Debugging
7. Document Revision History for the P-tile Avalon® Memory-mapped Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers

4.9. Configuration Output Interface

The Transaction Layer configuration output (tl_cfg) bus provides a subset of the information stored in the Configuration Space. Use this information in conjunction with the app_err* signals to understand TLP transmission problems.

Table 53.  Configuration Output Interface
Signal Name Direction Description Clock Domain EP/RP
tl_cfg_ctl_o[15:0] O Multiplexed data output from the register specified by tl_cfg_add_o[4:0]. The detailed information for each field in this bus is defined in the following table. p<n>_app_clk EP/RP
tl_cfg_add_o[4:0] O This address bus contains the index indicating which Configuration Space register information is being driven onto the tl_cfg_ctl_o[15:0] bits. p<n>_app_clk EP/RP

x16/x8: tl_cfg_func_o[2:0]

x4: NA

 O Specifies the function whose Configuration Space register values are being driven out on tl_cfg_ctl_o[15:0].
  • 3'b000: Physical Function 0 (PF0)
  • 3'b001: PF1

and so on

Note: In the 19.4 release of Intel® Quartus® Prime, the P-Tile Avalon® -MM IP only supports PF0.
p<n>_app_clk EP/RP

The table below provides the tl_cfg_add_o[4:0] to tl_cfg_ctl_o[15:0] mapping.

Table 54.  Multiplexed Configuration Information Available on tl_cfg_ctl
tl_cfg_add_o[4:0] tl_cfg_ctl_o[15:8] tl_cfg_ctl_o[7:0]
5'h00

[15]: memory space enable

[14]: IDO completion enable

[13]: perr_en

[12]: serr_en

[11]: fatal_err_rpt_en

[10]: nonfatal_err_rpt_en

[9]: corr_err_rpt_en

[8]: unsupported_req_rpt_en

Device control:

[7]: bus master enable

[6]: extended tag enable

[5:3]: maximum read request size

[2:0]: maximum payload size
5'h01

[15]: IDO request enable

[14]: No Snoop enable

[13]: Relaxed Ordering enable

[12:8]: Device number

 bus number
5'h02

[15]: pm_no_soft_rst

[14]: RCB control

[13]: Interrupt Request (IRQ) disable

[12:8]: PCIe Capability IRQ message number

[7:5]: reserved

[4]: system power control

[3:2]: system attention indicator control

[1:0]: system power indicator control
5'h03 Number of VFs [15:0]
5'h04

[15]: reserved

[14]: AtomicOP Egress Block field (cfg_atomic_egress_block)

[13:9]: ATS Smallest Translation Unit (STU)[4:0]

[8]: ATS cache enable

[7]: ARI forward enable

[6]: Atomic request enable

[5:3]: TPH ST mode

[2:1]: TPH enable

[0]: VF enable
5'h05
[15:12]: auto negotiation link speed. Link speed encoding values are:
  • Gen1 : 0x1
  • Gen2 : 0x2
  • Gen3 : 0x4
  • Gen4 : 0x8

[11:1]: Index of Start VF [10:0]

[0]: reserved

  
5'h06 MSI Address [15:0]
5'h07 MSI Address [31:16]
5'h08 MSI Address [47:32]
5'h09 MSI Address [63:48]
5'h0A MSI Mask [15:0]
5'h0B MSI Mask [31:16]
5'h0C

[15]: cfg_send_f_err

[14]: cfg_send_nf_err

[13]: cfg_send_cor_err

[12:8]: AER IRQ message number

[7]: Enable extended message data for MSI (cfg_msi_ext_data_en)

[6]: MSI-X func mask

[5]: MSI-X enable

[4:2]: Multiple MSI enable

[1]: 64-bit MSI

[0]: MSI enable
5'h0D MSI Data [15:0]  
5'h0E AER uncorrectable error mask [15:0]
5'h0F AER uncorrectable error mask [31:16]
5'h10 AER correctable error mask [15:0]
5'h11 AER correctable error mask [31:16]
5'h12 AER uncorrectable error severity [15:0]
5'h13 AER uncorrectable error severity [31:16]
5'h14 [15:8]: ACS Egress Control Register (cfg_acs_egress_ctrl_vec)

[7]: ACS function group enable (cfg_acs_func_grp_en)

[6]: ACS direct translated P2P enable (cfg_acs_p2p_direct_tranl_en)

[5]: ACS P2P egress control enable (cfg_acs_egress_ctrl_en)

[4]: ACS upstream forwarding enable (cfg_acs_up_forward_en)

[3]: ACS P2P completion redirect enable (cfg_acs_p2p_compl_redirect_en)

[2]: ACS P2P request redirect enable (cfg_acs_p2p_req_redirect_en)

[1]: ACS translation blocking enable (cfg_acs_at_blocking_en)

[0]: ACS source validation enable (RP) (cfg_acs_validation_en)

5'h15

[15]: reserved

[14]: 10-bit tag requester enable (cfg_10b_tag_req_en)

[13]: VF 10-bit tag requester enable (cfg_vf_10b_tag_req_en)

[12]: PRS_RESP_FAILURE (cfg_prs_response_failure)

[11]: PRS_UPRGI (cfg_prs_uprgi)

[10]: PRS_STOPPED (cfg_prs_stopped)

[9]: PRS_RESET (cfg_prs_reset)

[8]: PRS_ENABLE (cfg_prs_enable)

[7:3]: reserved

[2:0]: ARI function group (cfg_ari_func_grp)

5'h16 PRS_OUTSTANDING_ALLOCATION (cfg_prs_outstanding_allocation) [15:0]  
5'h17 PRS_OUTSTANDING_ALLOCATION (cfg_prs_outstanding_allocation) [31:16]  
5'h18

[15:10]: reserved

[9]: Disable autonomous generation of LTR clear message (cfg_disable_ltr_clr_msg)

[8]: LTR mechanism enable (cfg_ltr_m_en)

[7]: Infinite credits for Posted header

[6]: Infinite credits for Posted data

[5]: Infinite credits for Completion header

[4]: Infinite credits for Completion data

[3]: End-end TLP prefix blocking (cfg_end2end_tlp_pfx_blck)

[2]: PASID enable (cfg_pf_pasid_en)

[1]: Execute permission enable (cfg_pf_passid_execute_perm_en )

[0]: Privileged mode enable (cfg_pf_passid_priv_mode_en)

5'h19

[15:9]: reserved

[8]: Slot control attention button pressed enable (cfg_atten_button_pressed_en)

[7]: Slot control power fault detect enable (cfg_pwr_fault_det_en)

[6]: Slot control MRL sensor changed enable (cfg_mrl_sensor_chged_en)

[5]: Slot control presence detect changed enable (cfg_pre_det_chged_en)

[4]: Slot control hot plug interrupt enable (cfg_hp_int_en)

[3]: Slot control command completed interrupt enable (cfg_cmd_cpled_int_en)

[2]: Slot control DLL state change enable (cfg_dll_state_change_en)

[1]: Slot control accessed (cfg_hp_slot_ctrl_access)

[0]: PF’s SERR# enable (cfg_br_ctrl_serren)

5'h1A LTR maximum snoop latency register (cfg_ltr_max_latency[15:0])  
5'h1B LTR maximum no-snoop latency register (cfg_ltr_max_latency[31:16])  
5'h1C [15:8]: enabled Traffic Classes (TCs) (cfg_tc_enable[7:0])

[5:0]: auto negotiation link width

6’h01 = x1

6’h02 = x2

6’h04 = x4

6’h08 = x8

6’h10 = x16
5'h1D MSI Data[31:16]
5'h1E N/A
5'h1F N/A
Note:

The information on the Configuration Output (tl_cfg) bus is time-division multiplexed (TDM).

  • When tl_cfg_func[2:0] = 3'b000, tl_cfg_ctl[31:0] drive out the PF0 Configuration Space register values.
  • Then, tl_cfg_func[2:0] are incremented to 3'b001.
  • When tl_cfg_func[2:0] = 3'b001, tl_cfg_ctl[31:0] drive out the PF1 Configuration Space register values.
  • This pattern repeats to cover all enabled PFs.
  • The P-Tile Avalon® -MM IP for PCIe only supports PF0.
Figure 26. Configuration Output Interface Timing Diagram
Level Two Title