P-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express 2. IP Architecture and Functional Description 3. Parameters 4. Interfaces 5. Advanced Features 6. Troubleshooting/Debugging 7. Document Revision History for the P-tile Avalon® Memory-mapped Intel FPGA IP for PCI Express User Guide A. Configuration Space Registers
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express x
1.1. Overview 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Performance and Resource Utilization 1.6. IP Core and Design Example Support Levels
2. IP Architecture and Functional Description x
2.1. Top-Level Architecture 2.2. Functional Description
2.1. Top-Level Architecture x
2.1.1. Avalon® -MM Bridge Architecture 2.1.2. Clock Domains 2.1.3. Refclk 2.1.4. Reset
2.2. Functional Description x
2.2.1. PMA/PCS 2.2.2. Data Link Layer Overview 2.2.3. Transaction Layer Overview 2.2.4. Avalon® -MM Bridge
2.2.4. Avalon® -MM Bridge x
2.2.4.1. Endpoint Mode with Data Movers 2.2.4.2. Endpoint Mode 2.2.4.3. Root Port Mode
3. Parameters x
3.1. Top-Level Settings 3.2. Core Parameters 3.3. Avalon-MM Settings
3.2. Core Parameters x
3.2.1. Base Address Registers 3.2.2. PCI Express and PCI Capabilities Parameters 3.2.3. Device Identification Registers 3.2.4. Configuration, Debug and Extension Options
3.2.2. PCI Express and PCI Capabilities Parameters x
3.2.2.1. Device Capabilities 3.2.2.2. Link Capabilities 3.2.2.3. Legacy Interrupt Pin Register 3.2.2.4. MSI Capabilities 3.2.2.5. MSI-X Capabilities 3.2.2.6. Device Serial Number Capability 3.2.2.7. TLP Processing Hints (TPH)
4. Interfaces x
4.1. Overview 4.2. Clocks and Resets 4.3. Avalon® -MM Interface 4.4. Serial Data Interface 4.5. Hard IP Status Interface 4.6. Interrupt Interface 4.7. Hot Plug Interface (RP Only) 4.8. Power Management Interface 4.9. Configuration Output Interface 4.10. Hard IP Reconfiguration Interface 4.11. PHY Reconfiguration Interface
4.2. Clocks and Resets x
4.2.1. Interface Clock Signals 4.2.2. Interface Reset Signals
4.3. Avalon® -MM Interface x
4.3.1. Endpoint Mode Interface (512-bit Avalon® -MM Interface) 4.3.2. Root Port Mode Interface (256-bit Avalon® -MM Interface)
4.3.1. Endpoint Mode Interface (512-bit Avalon® -MM Interface) x
4.3.1.1. Bursting Avalon® -MM Master and Conduit 4.3.1.2. Bursting Avalon® -MM Slave and Conduit 4.3.1.3. Read Data Mover 4.3.1.4. Write Data Mover 4.3.1.5. Descriptor Format for Data Movers 4.3.1.6. Avalon® -MM DMA Operations
4.3.1.1. Bursting Avalon® -MM Master and Conduit x
4.3.1.1.1. Bursting Avalon® -MM Master and Conduit in Non-Bursting Mode
4.3.1.2. Bursting Avalon® -MM Slave and Conduit x
4.3.1.2.1. Bursting Avalon® -MM Slave and Conduit in Non-Bursting Mode
4.3.1.3. Read Data Mover x
4.3.1.3.1. Read Data Mover Avalon® -MM Write Master and Conduit 4.3.1.3.2. Read Data Mover Avalon® -ST Descriptor Sinks 4.3.1.3.3. Read Data Mover Status Avalon® -ST Source
4.3.1.4. Write Data Mover x
4.3.1.4.1. Write Data Mover Avalon® -MM Read Master and Conduit 4.3.1.4.2. Write Data Mover Avalon® -ST Descriptor Sinks 4.3.1.4.3. Write Data Mover Status Avalon® -ST Source
4.3.2. Root Port Mode Interface (256-bit Avalon® -MM Interface) x
4.3.2.1. High Performance Avalon® -MM Slave (HPTXS) Interface 4.3.2.2. High Performance Avalon® -MM Master (HPRXM) Interface 4.3.2.3. 32-Bit Control Register Access (CRA) Slave (Root Port only)
4.6. Interrupt Interface x
4.6.1. Legacy Interrupts 4.6.2. MSI 4.6.3. MSI-X
4.6.3. MSI-X x
4.6.3.1. Implementing MSI-X Interrupts
4.10. Hard IP Reconfiguration Interface x
4.10.1. Address Map for the User Avalon-MM Interface 4.10.2. Configuration Registers Access
4.10.2. Configuration Registers Access x
4.10.2.1. Using Direct User Avalon-MM Interface (Byte Access) 4.10.2.2. Using the Debug Register Interface Access
5. Advanced Features x
5.1. PCIe* Port Bifurcation and PHY Channel Mapping
6. Troubleshooting/Debugging x
6.1. Hardware 6.2. Debug Toolkit
6.1. Hardware x
6.1.1. Debugging Link Training Issues 6.1.2. Debugging Data Transfer and Performance Issues
6.1.1. Debugging Link Training Issues x
6.1.1.1. Generic Tools and Utilities 6.1.1.2. SignalTapII Logic Analyzer 6.1.1.3. Additional Debug Tools
6.1.2. Debugging Data Transfer and Performance Issues x
6.1.2.1. Advanced Error Reporting (AER) 6.1.2.2. Second-Level Debug Tools
6.2. Debug Toolkit x
6.2.1. Overview 6.2.2. Enabling the P-Tile Debug Toolkit 6.2.3. Launching the P-Tile Debug Toolkit 6.2.4. Using the P-Tile Debug Toolkit 6.2.5. Enabling the P-Tile Link Inspector 6.2.6. Using the P-Tile Link Inspector
A. Configuration Space Registers x
A.1. Configuration Space Registers A.2. Intel-Defined VSEC Capability Registers
A.1. Configuration Space Registers x
A.1.1. Register Access Definitions A.1.2. PCIe Configuration Header Registers A.1.3. PCI Express Capability Structures A.1.4. Physical Layer 16.0 GT/s Extended Capability Structure A.1.5. MSI-X Registers
A.2. Intel-Defined VSEC Capability Registers x
A.2.1. Intel-Defined VSEC Capability Header (Offset 00h) A.2.2. Intel-Defined Vendor Specific Header (Offset 04h) A.2.3. Intel Marker (Offset 08h) A.2.4. JTAG Silicon ID (Offset 0x0C - 0x18) A.2.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D) A.2.6. General Purpose Control and Status Register (Offset 0x30) A.2.7. Uncorrectable Internal Error Status Register (Offset 0x34) A.2.8. Uncorrectable Internal Error Mask Register (Offset 0x38) A.2.9. Correctable Internal Error Status Register (Offset 0x3C) A.2.10. Correctable Internal Error Mask Register (Offset 0x40)
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express
2. IP Architecture and Functional Description
3. Parameters
4. Interfaces
5. Advanced Features
6. Troubleshooting/Debugging
7. Document Revision History for the P-tile Avalon® Memory-mapped Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers

6.1.1.3. Additional Debug Tools

Use the Hard IP reconfiguration interface and PHY reconfiguration interface on the P-Tile Avalon® -MM IP for PCI Express to access additional registers (for example, receiver detection, lane reversal etc.).

Figure 37. Register Access for Debug

Using the Hard IP Reconfiguration Interface

Refer to the section Hard IP Reconfiguration Interface for details on this interface and the associated address map.

The following table lists the address offsets and bit settings for the PHY status registers. Use the Hard IP Reconfiguration Interface to access these read-only registers.

Table 62.  Hard IP Reconfiguration Interface Register Map for PHY Status
Offset Bit Position Register
0x0003E9 [0] RX polarity
[1] RX detection
[2] RX Valid
[3] RX Electrical Idle
[4] TX Electrical Idle
0x0003EC [7] Framing error
0x0003ED [7] Lane reversal
Follow the steps below to access registers in Table 62 using the Hard IP reconfiguration interface:
  1. Enable the Hard IP reconfiguration interface (User Avalon® -MM interface) using the IP Parameter Editor.
  2. Set the lane number for which you want to read the status by performing a read-modify-write to the address hip_reconfig_addr_i[20:0] with write data of lane number on hip_reconfig_writedata_i[7:0] using the Hard IP reconfiguration interface signals.
    • hip_reconfig_write_i = 1’b1
    • hip_reconfig_addr_i[20:0] = 0x0003E8
    • hip_reconfig_writedata_i[3:0] = <Lane number>, where Lane number = 4’h0 for lane 0, 4’h1 for lane 1, 4’h2 for lane 2, …
  3. Read the status of the register you want by performing a read operation from the address hip_reconfig_addr_i[20:0] using the Hard IP reconfiguration interface signals.
    • hip_reconfig_read_i = 1’b1
    • hip_reconfig_addr_i[20:0] = <offset>

      Offset = Refer to Table 62 for the offset mapping.

    • hip_reconfig_readdata_o[7:0] = Refer to Table 62 for the bit position mapping.
Example 1: To read the RX detection status of Lane0 using the registers
  1. Enable the Hard IP reconfiguration interface using the IP Parameter Editor.
  2. Perform read-modify-write to address 0x0003E8 to set the lane number to 0 using the Hard IP reconfiguration interface signals.
    • hip_reconfig_write_i = 1’b1
    • hip_reconfig_addr_i[20:0] = 0x0003E8
    • hip_reconfig_writedata_i[3:0] = 4'h0
  3. Read the status of the RX detection register by performing a read operation from the address 0x0003E9[1] using the Hard IP reconfiguration interface signals.
    • hip_reconfig_read_i = 1’b1
    • hip_reconfig_addr_i[20:0] = 0x0003E9
    • hip_reconfig_readdata_o[1] = 1'b1 (Far end receiver detected)

Using the PHY Reconfiguration Interface

Refer to the section PHY Reconfiguration Interface for details on how to use this interface.

Follow the steps below to access registers in Table 63 using the PHY reconfiguration interface.

  1. Enable the PHY reconfiguration interface using the IP Parameter Editor.
  2. Set the Quad and address offset from which you want to read the status by performing a read operation from the address xcvr_reconfig_addr_i[25:0] using the PHY reconfiguration interface signals.
    • xcvr_reconfig_read_i = 1’b1
    • xcvr_reconfig_addr_i[25:0] = {5-bit Quad mapping, 21-bit address offset}. Refer to Table 63 for the address offset and bit mapping.
    • xcvr_reconfig_readdata_o[7:0] = Refer to Table 63 for the address offset and bit mapping.
Table 63.  PHY Reconfiguration Interface Register Map for PHY Status
PHY Offset Bit Position Register
0x000006 [7]

PLLA state output status signal.

1'b1 indicates that PLLA is locked.
0x00000a [7]

PLLB state output status signal.

1'b1 indicates that PLLB is locked.
Example 2: To read the PLLA status using the registers
  1. Enable the PHY reconfiguration interface using the IP Parameter Editor.
  2. Perform a read from address 0x000006 to read the PLLA status output of Quad0 using the PHY reconfiguration interface signals.
    • xcvr_reconfig_read_i = 1'b1
    • xcvr_reconfig_addr_i[25:0] = 0x000006
    • xcvr_reconfig_readdata_o[7:0] = 8'h80
    • xcvr_reconfig_readdata_i = 1'b1 (PLLA state output high indicating PLL lock)
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