AN 709: HPS SoC Boot Guide - Cyclone V SoC Development Kit

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ID 683265
Date 1/27/2016
Public
Document Table of Contents
Document Table of Contents x
1. AN 709: HPS SoC Boot Guide - Cyclone V SoC Development Kit
1. AN 709: HPS SoC Boot Guide - Cyclone V SoC Development Kit x
1.1. Introduction 1.2. Boot Overview 1.3. Boot Duration 1.4. Boot Debugging 1.5. Boot Examples 1.6. Document Revision History
1.1. Introduction x
1.1.1. Prerequisite
1.2. Boot Overview x
1.2.1. Boot Flow 1.2.2. Boot Sources 1.2.3. Boot Clocks
1.2.1. Boot Flow x
1.2.1.1. Boot ROM 1.2.1.2. Preloader 1.2.1.3. Bootloader
1.2.2. Boot Sources x
1.2.2.1. Boot from SD/MMC 1.2.2.2. Boot from QSPI 1.2.2.3. Boot from NAND 1.2.2.4. Boot from FPGA 1.2.2.5. FPGA Fallback Boot 1.2.2.6. Boot from RAM on Warm Reset
1.3. Boot Duration x
1.3.1. Optimizing Boot Duration 1.3.2. Boot Duration Measurements
1.3.1. Optimizing Boot Duration x
1.3.1.1. Hardware Powerup Sequence 1.3.1.2. Boot ROM 1.3.1.3. Preloader 1.3.1.4. Bootloader 1.3.1.5. Linux Kernel 1.3.1.6. Init Scripts
1.4. Boot Debugging x
1.4.1. Boot ROM 1.4.2. Preloader 1.4.3. U-Boot
1.4.2. Preloader x
1.4.2.1. Debugging the Preloader from ARM DS-5 AE
1.5. Boot Examples x
1.5.1. Bare-Metal Application 1.5.2. Booting from SD/MMC – Custom Partition 1.5.3. Booting from SD/MMC – FAT Partition 1.5.4. Booting from QSPI Flash 1.5.5. Booting from FPGA
1.5.5. Booting from FPGA x
1.5.5.1. Overview 1.5.5.2. Hardware Design 1.5.5.3. Building and Running the Example
1. AN 709: HPS SoC Boot Guide - Cyclone V SoC Development Kit

1.5.5.1. Overview

In this example, we have the Preloader running from FPGA, but then it loads the bare-metal image that we have on SD/MMC custom partition. If desired, the Preloader can also be configured to jump to an absolute address, that may also be located in the FPGA fabric address space.

The boot flow of this example is described below:

Figure 12. Boot Flow

In order to achieve booting from FPGA the following are required:

  • BSEL needs to be set to 0x1 - Boot from FPGA
  • FPGA image needs to have an on-chip memory instantiated, mapped at offset 0x0 behind the HPS2FPGA bridge. The memory needs to be loaded with Preloader executable binary
  • FPGA image needs to drive the value of the following two signals to HPS, since they are required by Boot ROM:
    • f2h_boot_from_fpga_ready - indicates that the Boot ROM can boot from FPGA if BSEL = 0x1
    • f2h_boot_from_fpga_on_failure - indicates that the Boot ROM can boot from FPGA as a fallback, if it failed booting from the selected BSEL
  • Preloader executable (.text) section needs to be linked to address 0xC0000000 (equivalent of offset 0x0 behind the HPS2FPGA bridge)
  • Preloader executable (.data) sections need to be linked to address 0xFFFF0000 (the HPS OCRAM)

The complete flow is described in the following figure:

Figure 13. Complete Flow
Note: The design needs to be compiled once in order to obtain the handoff folder, which is used to generate the Preloader. Once the Preloader hex file is obtained, the design is compiled again in order to have the FPGA memory initialized with the contents of the hex file.
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