AN 709: HPS SoC Boot Guide - Cyclone V SoC Development Kit

Download PDF
ID 683265
Date 1/27/2016
Public
Document Table of Contents
Document Table of Contents x
1. AN 709: HPS SoC Boot Guide - Cyclone V SoC Development Kit
1. AN 709: HPS SoC Boot Guide - Cyclone V SoC Development Kit x
1.1. Introduction 1.2. Boot Overview 1.3. Boot Duration 1.4. Boot Debugging 1.5. Boot Examples 1.6. Document Revision History
1.1. Introduction x
1.1.1. Prerequisite
1.2. Boot Overview x
1.2.1. Boot Flow 1.2.2. Boot Sources 1.2.3. Boot Clocks
1.2.1. Boot Flow x
1.2.1.1. Boot ROM 1.2.1.2. Preloader 1.2.1.3. Bootloader
1.2.2. Boot Sources x
1.2.2.1. Boot from SD/MMC 1.2.2.2. Boot from QSPI 1.2.2.3. Boot from NAND 1.2.2.4. Boot from FPGA 1.2.2.5. FPGA Fallback Boot 1.2.2.6. Boot from RAM on Warm Reset
1.3. Boot Duration x
1.3.1. Optimizing Boot Duration 1.3.2. Boot Duration Measurements
1.3.1. Optimizing Boot Duration x
1.3.1.1. Hardware Powerup Sequence 1.3.1.2. Boot ROM 1.3.1.3. Preloader 1.3.1.4. Bootloader 1.3.1.5. Linux Kernel 1.3.1.6. Init Scripts
1.4. Boot Debugging x
1.4.1. Boot ROM 1.4.2. Preloader 1.4.3. U-Boot
1.4.2. Preloader x
1.4.2.1. Debugging the Preloader from ARM DS-5 AE
1.5. Boot Examples x
1.5.1. Bare-Metal Application 1.5.2. Booting from SD/MMC – Custom Partition 1.5.3. Booting from SD/MMC – FAT Partition 1.5.4. Booting from QSPI Flash 1.5.5. Booting from FPGA
1.5.5. Booting from FPGA x
1.5.5.1. Overview 1.5.5.2. Hardware Design 1.5.5.3. Building and Running the Example
1. AN 709: HPS SoC Boot Guide - Cyclone V SoC Development Kit

1.5.5.2. Hardware Design

This section presents a very simple hardware design that was used for this example. You need ACDS to be installed on your host PC to be able to reproduce this example.
Note: The design is already provided with this guide. It does not need to be re-created by the user. But it needs to be re-compiled if the Preloader hex file is changed.

The design is based on the Altera GHRD, with a reduced number of components:

  • HPS - Hard Processor Instance
  • SysID - System ID
  • HPS Boot Memory - FPGA memory used to store Preloader binary
  • Clk - Clock and Reset source

The following picture presents the System Contents view for the hardware design:

Figure 14. System Contents View for the Hardware Design

The HPS Component needs to be configured to enable the Boot from FPGA signals as shown in the screenshot below:

Figure 15. Enable Boot From FPGA Signals
The HPS Boot Memory needs to be set to 8-bit width, and be initialized with a hex file containing the Preloader image. The following screenshot show the memory settings that were used for this example.
Note: The Preloader image is stored in the file named software/spl_bsp/preloader.hex.
Figure 16. On-Chip Memory Parameters
Note:
  • The HPS bus f2h_boot_from_fpga was exported by double-clicking the corresponding cell in the Export column.
  • The HPS Boot Memory was connected to the h2f AXI bus.
  • The HPS Boot Memory was set to a base address of 0x0000000.
  • The f2h_boot_from_fpga signals need to be tied at the top level to the proper values. For this example, they were tied like this in the file rd_top.v:
    
// SoC sub-system module
soc_system soc_inst (  ... 
        .hps_0_f2h_boot_from_fpga_boot_from_fpga_ready         (1'b1), 
        .hps_0_f2h_boot_from_fpga_boot_from_fpga_on_failure    (1'b0));
Level Two Title