Quartus® Prime Pro Edition User Guide: Timing Analyzer

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ID 683243
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Timing Analysis Introduction 2. Using the Quartus® Prime Timing Analyzer A. Quartus® Prime Pro Edition User Guides
1. Timing Analysis Introduction x
1.1. What's New In This Version 1.2. Timing Analysis Basic Concepts 1.3. Timing Analysis Overview Document Revision History
1.2. Timing Analysis Basic Concepts x
1.2.1. Timing Path and Clock Analysis 1.2.2. Clock Setup Analysis 1.2.3. Clock Hold Analysis 1.2.4. Recovery and Removal Analysis 1.2.5. Multicycle Path Analysis 1.2.6. Metastability Analysis 1.2.7. Timing Pessimism 1.2.8. Clock-As-Data Analysis 1.2.9. Multicorner Timing Analysis 1.2.10. Time Borrowing
1.2.1. Timing Path and Clock Analysis x
1.2.1.1. The Timing Netlist 1.2.1.2. Timing Paths 1.2.1.3. Data and Clock Arrival Times 1.2.1.4. Launch and Latch Edges
1.2.5. Multicycle Path Analysis x
1.2.5.1. Multicycle Clock Hold 1.2.5.2. Multicycle Clock Setup
1.2.10. Time Borrowing x
1.2.10.1. Time Borrowing Limitations 1.2.10.2. Time Borrowing with Latches 1.2.10.3. Enabling Time Borrowing Optimization
2. Using the Quartus® Prime Timing Analyzer x
2.1. Using Timing Constraints throughout the Design Flow 2.2. Timing Analysis Flow 2.3. Applying Timing Constraints 2.4. Timing Constraint Descriptions 2.5. Timing Report Descriptions 2.6. Scripting Timing Analysis 2.7. Using the Quartus® Prime Timing Analyzer Document Revision History 2.8. Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
2.2. Timing Analysis Flow x
2.2.1. Step 1: Specify General Timing Analyzer Settings 2.2.2. Step 2: Specify Timing Constraints 2.2.3. Step 3: Run the Timing Analyzer 2.2.4. Step 4: Analyze Timing Reports
2.2.2. Step 2: Specify Timing Constraints x
2.2.2.1. Specifying SDC-on-RTL Timing Constraints 2.2.2.2. Specifying Conventional SDC Timing Constraints 2.2.2.3. Specifying Synthesis-Only SDC Timing Constraints
2.2.3. Step 3: Run the Timing Analyzer x
2.2.3.1. Running Post-Synthesis Early Timing Analysis 2.2.3.2. Running Post-Fit Timing Analysis
2.2.3.2. Running Post-Fit Timing Analysis x
2.2.3.2.1. Setting the Operating Conditions for Timing Analysis 2.2.3.2.2. Promoting Critical Warnings to Errors
2.2.4. Step 4: Analyze Timing Reports x
2.2.4.1. Cross-Probing with Design Assistant 2.2.4.2. Launching Design Assistant from Timing Analyzer 2.2.4.3. Locating Timing Paths in Other Tools 2.2.4.4. Correlating Constraints to the Timing Report
2.2.4.1. Cross-Probing with Design Assistant x
2.2.4.1.1. Cross-Probing from Design Assistant to Timing Analyzer
2.3. Applying Timing Constraints x
2.3.1. Recommended Initial Conventional SDC Constraints 2.3.2. Example Circuit and Conventional SDC File 2.3.3. SDC File Precedence 2.3.4. Iteratively Modifying Constraints 2.3.5. Applying Entity-Bound Timing Constraints 2.3.6. Constraining Design Partition Ports 2.3.7. Using Fitter Overconstraints Overconstraints for Stratix® 10 Designs Overconstraints for Designs that Target All Other Device Families Other Overconstraint Combinations
2.3.1. Recommended Initial Conventional SDC Constraints x
2.3.1.1. Create Clock (create_clock) 2.3.1.2. Derive PLL Clocks (derive_pll_clocks) 2.3.1.3. Derive Clock Uncertainty (derive_clock_uncertainty) 2.3.1.4. Set Clock Groups (set_clock_groups)
2.3.5. Applying Entity-Bound Timing Constraints x
2.3.5.1. Using Entity-Based SDC-on-RTL Constraints 2.3.5.2. Using Entity-Bound SDC Files
2.3.5.1. Using Entity-Based SDC-on-RTL Constraints x
2.3.5.1.1. Targeting Constraints to Module Inputs and Outputs 2.3.5.1.2. Entity Based SDC-on-RTL Constraint Scope 2.3.5.1.3. Automatic Scope Example for SDC-on-RTL 2.3.5.1.4. Manual Scope Example for SDC-on-RTL
2.3.5.2. Using Entity-Bound SDC Files x
2.3.5.2.1. Entity-Bound SDC Constraint Scope 2.3.5.2.2. Automatic Scope Entity-bound Constraint Example 2.3.5.2.3. Manual Scope Entity-bound Constraint Example 2.3.5.2.4. Exporting a Design Partition with Entity-bound Constraints 2.3.5.2.5. Importing a Design Partition with Entity-bound Constraints
2.3.6. Constraining Design Partition Ports x
2.3.6.1. Timing Analysis of Imported Compilation Results
2.4. Timing Constraint Descriptions x
2.4.1. Clock Constraints 2.4.2. I/O Constraints 2.4.3. Delay and Skew Constraints 2.4.4. Timing Exception Constraints 2.4.5. Delay Annotation
2.4.1. Clock Constraints x
2.4.1.1. Creating Base Clocks 2.4.1.2. Creating Virtual Clocks 2.4.1.3. Creating Generated Clocks (create_generated_clock) 2.4.1.4. Deriving PLL Clocks 2.4.1.5. Creating Clock Groups (set_clock_groups) 2.4.1.6. Accounting for Clock Effect Characteristics 2.4.1.7. Constraining CDC Paths
2.4.1.1. Creating Base Clocks x
2.4.1.1.1. Automatic Clock Detection and Constraint Creation
2.4.1.2. Creating Virtual Clocks x
2.4.1.2.1. Specifying I/O Interface Uncertainty 2.4.1.2.2. I/O Interface Clock Uncertainty Example
2.4.1.3. Creating Generated Clocks (create_generated_clock) x
2.4.1.3.1. Clock Divider Example (-divide_by) 2.4.1.3.2. Clock Multiplexer Example
2.4.1.5. Creating Clock Groups (set_clock_groups) x
2.4.1.5.1. Exclusive Clock Groups (-logically_exclusive or -physically_exclusive) 2.4.1.5.2. Asynchronous Clock Groups (-asynchronous) 2.4.1.5.3. set_clock_groups Constraint Tips
2.4.1.6. Accounting for Clock Effect Characteristics x
2.4.1.6.1. Set Clock Latency (set_clock_latency) 2.4.1.6.2. Clock Uncertainty
2.4.2. I/O Constraints x
2.4.2.1. Input Constraints (set_input_delay) 2.4.2.2. Output Constraints (set_output_delay)
2.4.3. Delay and Skew Constraints x
2.4.3.1. Advanced I/O Timing and Board Trace Model Delay 2.4.3.2. Maximum Skew (set_max_skew) 2.4.3.3. Net Delay (set_net_delay)
2.4.4. Timing Exception Constraints x
2.4.4.1. Timing Exception Precedence 2.4.4.2. False Paths (set_false_path) 2.4.4.3. Minimum and Maximum Delays 2.4.4.4. Multicycle Paths 2.4.4.5. Multicycle Exception Examples
2.4.4.4. Multicycle Paths x
2.4.4.4.1. Common Multicycle Applications 2.4.4.4.2. Relaxing Setup with Multicycle (set_multicyle_path) 2.4.4.4.3. Accounting for a Phase Shift (-phase)
2.4.4.5. Multicycle Exception Examples x
2.4.4.5.1. Default Multicycle Analysis 2.4.4.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0 2.4.4.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1 2.4.4.5.4. Same Frequency Clocks with Destination Clock Offset 2.4.4.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency 2.4.4.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset 2.4.4.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency 2.4.4.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
2.5. Timing Report Descriptions x
2.5.1. Report Fmax Summary 2.5.2. Report Timing 2.5.3. Report Timing By Source Files 2.5.4. Report Data Delay 2.5.5. Report Net Delay 2.5.6. Report Clocks and Clock Network 2.5.7. Report Clock Transfers 2.5.8. Report Metastability 2.5.9. Report CDC Viewer 2.5.10. Report Asynchronous CDC 2.5.11. Report Logic Depth 2.5.12. Report Neighbor Paths 2.5.13. Report Register Spread 2.5.14. Report Route Net of Interest 2.5.15. Report Retiming Restrictions 2.5.16. Report Register Statistics 2.5.17. Report Pipelining Information 2.5.18. Report Time Borrowing Data 2.5.19. Report Exceptions and Exceptions Reachability 2.5.20. Report Bottlenecks 2.5.21. Check Timing 2.5.22. Report SDC
2.5.13. Report Register Spread x
2.5.13.1. Registers with High Timing Path Endpoint Tension 2.5.13.2. Registers with High Immediate Fan-Out Tension
2.5.20. Report Bottlenecks x
2.5.20.1. Specifying Custom Bottleneck Criteria
2.6. Scripting Timing Analysis x
2.6.1. The quartus_sta Executable 2.6.2. The quartus_staw Executable 2.6.3. Collection Commands
2.6.3. Collection Commands x
2.6.3.1. Wildcard Characters 2.6.3.2. Adding and Removing Collection Items 2.6.3.3. Query of Collections 2.6.3.4. Using the get_pins Command
Answers to Top FAQs
1. Timing Analysis Introduction
2. Using the Quartus® Prime Timing Analyzer
A. Quartus® Prime Pro Edition User Guides

2.3.7. Using Fitter Overconstraints

Fitter overconstraints are timing constraints that you adjust to overcome modeling inaccuracies, mis-correlation, or other deficiencies in logic optimization. You can overconstrain setup and hold paths in the Fitter to enable more aggressive timing optimization of specific paths.

Overconstraints for Stratix® 10 Designs

One typically writes overconstraints that apply only during the Fitter, with a conditional statement that checks the name of the executable that is reading the .sdc file. The following example shows a conditional statement that applies an overconstraint during the Fitter. 

# Example Fitter overconstraint targeting specific nodes
if { $::TimingAnalyzerInfo(nameofexecutable) eq "quartus_fit"} {
  set_max_delay -from ${my_src_regs} -to ${my_dst_regs} 1ns
}

One typically applies overconstraints because a particular path (or set of paths) requires more than the default optimization effort from the Fitter. Therefore, overconstraints typically specify particular node or register names in the path or paths that require extra optimization.

For devices that support the Hyperflex® architecture, such as Stratix® 10 and Agilex™ FPGA portfolio devices, timing constraints that apply to particular node or register names prevent the Hyper-Retimer from optimizing paths containing those nodes or registers.

Because the Hyper-Retimer is component of the Fitter, an overconstraint that conditionally applies during the Fitter is counter-productive during the Hyper-Retimer portion of the Fitter. The overconstraint actually prevents the optimization instead of focusing the optimization effectively.

When designing for the Hyperflex® architecture, use the is_post_route Tcl function form of conditional statement to apply the overconstraint during placement and routing but not during the Hyper-Retimer. is_post_route allows you to apply overconstraints and adjust slack for stages of the Fitter, such as Plan, Place, and Route. is_post_route also allows post-route retiming via the Hyper-Retimer without affecting sign-off timing analysis. 

# Example Fitter overconstraint targeting specific nodes (allows for post-route retiming)
if { ! [is_post_route]} {
  set_max_delay -from ${my_src_regs} -to ${my_dst_regs} 1ns
}
Note: The is_post_route function is inclusive. To exclude the function, use the negation syntax (!).

Overconstraints for Designs that Target All Other Device Families

You can assign Fitter overconstraints that check the name of the current executable, (either quartus_fit or quartus_sta) to apply different constraints for Fitter optimization and sign-off timing analysis. 

set fit_flow 0
if { $::TimingAnalyzerInfo(nameofexecutable) == "quartus_fit" } {
   set fit_flow 1
}
if {$fit_flow} {
  # Example Fitter overconstraint targeting specific nodes (restricts retiming)
  set_max_delay -from ${my_src_regs} -to ${my_dst_regs} 1ns
}

Other Overconstraint Combinations

You can apply timing constraints to specific stages of the Compiler, in addition to the Fitter as described above. The following table shows different combinations of compile stages and the conditional expression that applies those constraints during the stage or stages.

Table 13.  Overconstraint Combinations
Compile Stages Tcl Condition Notes
Fitter if { $::TimingAnalyzerInfo(nameofexecutable) eq "quartus_fit" } Applies constraints during entire Fitter stage. Use for fitter overconstraints with devices that do not support Hyperflex® architecture.
Signoff timing if { $::TimingAnalyzerInfo(nameofexecutable) eq "quartus_sta" } Applies constraints during timing analysis. This condition is uncommon. Typically you apply timing analysis constraints during the entire compile flow.
Plan, Place, and Route if { ! [is_post_route] } Applies constraints during the Plan, Place, and Route stages in devices that support the Hyperflex® architecture. Use for fitter overconstraints .
Retime (HyperRetimer), Finalize, Signoff timing if { [is_post_route] } Applies constraints after the Route stage completes in devices that support the Hyperflex® architecture. This combination of stages is uncommon. Typically you apply timing analysis constraints during the entire compile flow.
Retime (HyperRetimer) and Finalize if { [is_post_route] && $::TimingAnalyzerInfo(nameofexecutable) eq "quartus_fit" } Applies constraints during Retiming and Finalize stages in devices that support the Hyperflex® architecture. This combination of stages is uncommon.
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