Quartus® Prime Pro Edition User Guide: Timing Analyzer

Download PDF
ID 683243
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Timing Analysis Introduction 2. Using the Quartus® Prime Timing Analyzer A. Quartus® Prime Pro Edition User Guides
1. Timing Analysis Introduction x
1.1. What's New In This Version 1.2. Timing Analysis Basic Concepts 1.3. Timing Analysis Overview Document Revision History
1.2. Timing Analysis Basic Concepts x
1.2.1. Timing Path and Clock Analysis 1.2.2. Clock Setup Analysis 1.2.3. Clock Hold Analysis 1.2.4. Recovery and Removal Analysis 1.2.5. Multicycle Path Analysis 1.2.6. Metastability Analysis 1.2.7. Timing Pessimism 1.2.8. Clock-As-Data Analysis 1.2.9. Multicorner Timing Analysis 1.2.10. Time Borrowing
1.2.1. Timing Path and Clock Analysis x
1.2.1.1. The Timing Netlist 1.2.1.2. Timing Paths 1.2.1.3. Data and Clock Arrival Times 1.2.1.4. Launch and Latch Edges
1.2.5. Multicycle Path Analysis x
1.2.5.1. Multicycle Clock Hold 1.2.5.2. Multicycle Clock Setup
1.2.10. Time Borrowing x
1.2.10.1. Time Borrowing Limitations 1.2.10.2. Time Borrowing with Latches 1.2.10.3. Enabling Time Borrowing Optimization
2. Using the Quartus® Prime Timing Analyzer x
2.1. Using Timing Constraints throughout the Design Flow 2.2. Timing Analysis Flow 2.3. Applying Timing Constraints 2.4. Timing Constraint Descriptions 2.5. Timing Report Descriptions 2.6. Scripting Timing Analysis 2.7. Using the Quartus® Prime Timing Analyzer Document Revision History 2.8. Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
2.2. Timing Analysis Flow x
2.2.1. Step 1: Specify General Timing Analyzer Settings 2.2.2. Step 2: Specify Timing Constraints 2.2.3. Step 3: Run the Timing Analyzer 2.2.4. Step 4: Analyze Timing Reports
2.2.2. Step 2: Specify Timing Constraints x
2.2.2.1. Specifying SDC-on-RTL Timing Constraints 2.2.2.2. Specifying Conventional SDC Timing Constraints 2.2.2.3. Specifying Synthesis-Only SDC Timing Constraints
2.2.3. Step 3: Run the Timing Analyzer x
2.2.3.1. Running Post-Synthesis Early Timing Analysis 2.2.3.2. Running Post-Fit Timing Analysis
2.2.3.2. Running Post-Fit Timing Analysis x
2.2.3.2.1. Setting the Operating Conditions for Timing Analysis 2.2.3.2.2. Promoting Critical Warnings to Errors
2.2.4. Step 4: Analyze Timing Reports x
2.2.4.1. Cross-Probing with Design Assistant 2.2.4.2. Launching Design Assistant from Timing Analyzer 2.2.4.3. Locating Timing Paths in Other Tools 2.2.4.4. Correlating Constraints to the Timing Report
2.2.4.1. Cross-Probing with Design Assistant x
2.2.4.1.1. Cross-Probing from Design Assistant to Timing Analyzer
2.3. Applying Timing Constraints x
2.3.1. Recommended Initial Conventional SDC Constraints 2.3.2. Example Circuit and Conventional SDC File 2.3.3. SDC File Precedence 2.3.4. Iteratively Modifying Constraints 2.3.5. Applying Entity-Bound Timing Constraints 2.3.6. Constraining Design Partition Ports 2.3.7. Using Fitter Overconstraints
2.3.1. Recommended Initial Conventional SDC Constraints x
2.3.1.1. Create Clock (create_clock) 2.3.1.2. Derive PLL Clocks (derive_pll_clocks) 2.3.1.3. Derive Clock Uncertainty (derive_clock_uncertainty) 2.3.1.4. Set Clock Groups (set_clock_groups)
2.3.5. Applying Entity-Bound Timing Constraints x
2.3.5.1. Using Entity-Based SDC-on-RTL Constraints 2.3.5.2. Using Entity-Bound SDC Files
2.3.5.1. Using Entity-Based SDC-on-RTL Constraints x
2.3.5.1.1. Targeting Constraints to Module Inputs and Outputs 2.3.5.1.2. Entity Based SDC-on-RTL Constraint Scope 2.3.5.1.3. Automatic Scope Example for SDC-on-RTL 2.3.5.1.4. Manual Scope Example for SDC-on-RTL
2.3.5.2. Using Entity-Bound SDC Files x
2.3.5.2.1. Entity-Bound SDC Constraint Scope 2.3.5.2.2. Automatic Scope Entity-bound Constraint Example 2.3.5.2.3. Manual Scope Entity-bound Constraint Example 2.3.5.2.4. Exporting a Design Partition with Entity-bound Constraints 2.3.5.2.5. Importing a Design Partition with Entity-bound Constraints
2.3.6. Constraining Design Partition Ports x
2.3.6.1. Timing Analysis of Imported Compilation Results
2.4. Timing Constraint Descriptions x
2.4.1. Clock Constraints 2.4.2. I/O Constraints 2.4.3. Delay and Skew Constraints 2.4.4. Timing Exception Constraints 2.4.5. Delay Annotation
2.4.1. Clock Constraints x
2.4.1.1. Creating Base Clocks 2.4.1.2. Creating Virtual Clocks 2.4.1.3. Creating Generated Clocks (create_generated_clock) 2.4.1.4. Deriving PLL Clocks 2.4.1.5. Creating Clock Groups (set_clock_groups) 2.4.1.6. Accounting for Clock Effect Characteristics 2.4.1.7. Constraining CDC Paths
2.4.1.1. Creating Base Clocks x
2.4.1.1.1. Automatic Clock Detection and Constraint Creation
2.4.1.2. Creating Virtual Clocks x
2.4.1.2.1. Specifying I/O Interface Uncertainty 2.4.1.2.2. I/O Interface Clock Uncertainty Example
2.4.1.3. Creating Generated Clocks (create_generated_clock) x
2.4.1.3.1. Clock Divider Example (-divide_by) 2.4.1.3.2. Clock Multiplexer Example
2.4.1.5. Creating Clock Groups (set_clock_groups) x
2.4.1.5.1. Exclusive Clock Groups (-logically_exclusive or -physically_exclusive) 2.4.1.5.2. Asynchronous Clock Groups (-asynchronous) 2.4.1.5.3. set_clock_groups Constraint Tips
2.4.1.6. Accounting for Clock Effect Characteristics x
2.4.1.6.1. Set Clock Latency (set_clock_latency) 2.4.1.6.2. Clock Uncertainty
2.4.2. I/O Constraints x
2.4.2.1. Input Constraints (set_input_delay) 2.4.2.2. Output Constraints (set_output_delay)
2.4.3. Delay and Skew Constraints x
2.4.3.1. Advanced I/O Timing and Board Trace Model Delay 2.4.3.2. Maximum Skew (set_max_skew) 2.4.3.3. Net Delay (set_net_delay)
2.4.4. Timing Exception Constraints x
2.4.4.1. Timing Exception Precedence 2.4.4.2. False Paths (set_false_path) 2.4.4.3. Minimum and Maximum Delays 2.4.4.4. Multicycle Paths 2.4.4.5. Multicycle Exception Examples
2.4.4.4. Multicycle Paths x
2.4.4.4.1. Common Multicycle Applications 2.4.4.4.2. Relaxing Setup with Multicycle (set_multicyle_path) 2.4.4.4.3. Accounting for a Phase Shift (-phase)
2.4.4.5. Multicycle Exception Examples x
2.4.4.5.1. Default Multicycle Analysis 2.4.4.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0 2.4.4.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1 2.4.4.5.4. Same Frequency Clocks with Destination Clock Offset 2.4.4.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency 2.4.4.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset 2.4.4.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency 2.4.4.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
2.5. Timing Report Descriptions x
2.5.1. Report Fmax Summary 2.5.2. Report Timing 2.5.3. Report Timing By Source Files 2.5.4. Report Data Delay 2.5.5. Report Net Delay 2.5.6. Report Clocks and Clock Network 2.5.7. Report Clock Transfers 2.5.8. Report Metastability 2.5.9. Report CDC Viewer 2.5.10. Report Asynchronous CDC 2.5.11. Report Logic Depth 2.5.12. Report Neighbor Paths 2.5.13. Report Register Spread 2.5.14. Report Route Net of Interest 2.5.15. Report Retiming Restrictions 2.5.16. Report Register Statistics 2.5.17. Report Pipelining Information 2.5.18. Report Time Borrowing Data 2.5.19. Report Exceptions and Exceptions Reachability 2.5.20. Report Bottlenecks 2.5.21. Check Timing 2.5.22. Report SDC
2.5.13. Report Register Spread x
2.5.13.1. Registers with High Timing Path Endpoint Tension 2.5.13.2. Registers with High Immediate Fan-Out Tension
2.5.20. Report Bottlenecks x
2.5.20.1. Specifying Custom Bottleneck Criteria
2.6. Scripting Timing Analysis x
2.6.1. The quartus_sta Executable 2.6.2. The quartus_staw Executable 2.6.3. Collection Commands
2.6.3. Collection Commands x
2.6.3.1. Wildcard Characters 2.6.3.2. Adding and Removing Collection Items 2.6.3.3. Query of Collections 2.6.3.4. Using the get_pins Command
Answers to Top FAQs
1. Timing Analysis Introduction
2. Using the Quartus® Prime Timing Analyzer
A. Quartus® Prime Pro Edition User Guides

1.2.5.1. Multicycle Clock Hold

The number of clock periods between the clock launch edge and the latch edge defines the setup relationship.

By default, the Timing Analyzer performs a single-cycle path analysis. When analyzing a path, the Timing Analyzer performs two hold checks. The first hold check determines that the data that launches from the current launch edge is not captured by the previous latch edge. The second hold check determines that the data that launches from the next launch edge is not captured by the current latch edge. The Timing Analyzer reports only the most restrictive hold check. The Timing Analyzer calculates the hold check by comparing launch and latch edges.

Figure 23. Hold CheckThe Timing Analyzer uses the following calculation to determine the hold check.
Tip: If a hold check overlaps a setup check, the hold check is ignored.

A start multicycle hold assignment modifies the launch edge of the source clock by moving the launch edge the number of clock periods you specify to the right of the default launch edge. The following figure shows various values of the start multicycle hold (SMH) assignment and the resulting launch edge.

Figure 24. Start Multicycle Hold Values

An end multicycle hold assignment modifies the latch edge of the destination clock by moving the latch edge the specific number of clock periods to the left of the default latch edge. The following figure shows various values of the end multicycle hold (EMH) assignment and the resulting latch edge.

Figure 25. End Multicycle Hold Values
Figure 26. End Multicycle Hold Values the Timing Analyzer ReportsThe following shows the hold relationship the Timing Analyzer reports for the negative hold relationship:
Level Two Title