Intel Agilex® 7 Embedded Memory User Guide

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ID 683241
Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 Embedded Memory Overview 2. Intel Agilex® 7 Embedded Memory Architecture and Features 3. Intel Agilex® 7 Embedded Memory Design Considerations 4. Intel Agilex® 7 Embedded Memory IP References 5. Intel Agilex® 7 Embedded Memory Debugging 6. Intel Agilex® 7 Embedded Memory User Guide Archives 7. Document Revision History for the Intel Agilex® 7 Embedded Memory User Guide
1. Intel Agilex® 7 Embedded Memory Overview x
1.1. Intel Agilex® 7 Embedded Memory Features
2. Intel Agilex® 7 Embedded Memory Architecture and Features x
2.1. Fabric Network-On-Chip (NoC) in Intel Agilex® 7 M-Series M20K Blocks 2.2. Byte Enable in Intel Agilex® 7 Embedded Memory Blocks 2.3. Address Clock Enable Support 2.4. Asynchronous Clear and Synchronous Clear 2.5. Memory Blocks Error Correction Code (ECC) Support 2.6. Intel Agilex® 7 Embedded Memory Clocking Modes 2.7. Intel Agilex® 7 Embedded Memory Configurations 2.8. Force-to-Zero 2.9. Coherent Read Memory 2.10. Freeze Logic 2.11. True Dual Port Dual Clock Emulator 2.12. Initial Value of Read and Write Address Registers 2.13. Timing/Power Optimization Feature in M20K Blocks 2.14. Intel Agilex® 7 Supported Embedded Memory IPs
2.2. Byte Enable in Intel Agilex® 7 Embedded Memory Blocks x
2.2.1. Byte Enable Controls 2.2.2. Data Byte Output 2.2.3. Byte Enable Behavior
2.5. Memory Blocks Error Correction Code (ECC) Support x
2.5.1. Parity Bit 2.5.2. ECC Parity Flip 2.5.3. ECC Read-During-Write Behavior 2.5.4. Error Correction Code Truth Table
2.6. Intel Agilex® 7 Embedded Memory Clocking Modes x
2.6.1. Single Clock Mode 2.6.2. Read/Write Clock Mode 2.6.3. Input/Output Clock Mode 2.6.4. Asynchronous/Synchronous Clears in Clocking Modes 2.6.5. Output Read Data in Simultaneous Read/Write 2.6.6. Independent Clock Enables in Clocking Modes
2.7. Intel Agilex® 7 Embedded Memory Configurations x
2.7.1. Mixed-Width Port Configurations
2.9. Coherent Read Memory x
2.9.1. Forwarding Logic
3. Intel Agilex® 7 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Read Behavior 3.3. Customize Read-During-Write Behavior 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Advanced Settings in Intel® Quartus® Prime Software for Memory 3.9. Consider the Memory Depth Setting 3.10. Consider Registering the Memory Output
3.3. Customize Read-During-Write Behavior x
3.3.1. Same-Port Read-During-Write Mode 3.3.2. Mixed-Port Read-During-Write Mode
4. Intel Agilex® 7 Embedded Memory IP References x
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores 4.2. eSRAM Intel Agilex® FPGA IP 4.3. FIFO Intel® FPGA IP 4.4. Shift Register (RAM-based) Intel® FPGA IP
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores x
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs 4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters 4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters 4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters 4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters 4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters 4.1.7. Changing Parameter Settings Manually 4.1.8. RAM and ROM Interface Signals
4.1.7. Changing Parameter Settings Manually x
4.1.7.1. RAM and ROM Parameter Settings
4.2. eSRAM Intel Agilex® FPGA IP x
4.2.1. Release Information for eSRAM Intel Agilex® FPGA IP 4.2.2. eSRAM System Features 4.2.3. eSRAM Intel Agilex® FPGA IP Parameters 4.2.4. eSRAM Intel Agilex® FPGA IP Interface Signals 4.2.5. eSRAM Timing Diagrams
4.2.2. eSRAM System Features x
4.2.2.1. eSRAM Specifications
4.3. FIFO Intel® FPGA IP x
4.3.1. Release Information for FIFO Intel® FPGA IP 4.3.2. Configuration Methods 4.3.3. Specifications 4.3.4. FIFO Functional Timing Requirements 4.3.5. SCFIFO ALMOST_EMPTY Functional Timing 4.3.6. FIFO Output Status Flag and Latency 4.3.7. FIFO Metastability Protection and Related Options 4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.3.9. SCFIFO and DCFIFO Show-Ahead Mode 4.3.10. Different Input and Output Width 4.3.11. DCFIFO Timing Constraint Setting 4.3.12. Coding Example for Manual Instantiation 4.3.13. Design Example 4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing 4.3.15. Guidelines for Embedded Memory ECC Feature 4.3.16. FIFO Intel® FPGA IP Parameters 4.3.17. Reset Scheme
4.3.3. Specifications x
4.3.3.1. Verilog HDL Prototype 4.3.3.2. VHDL Component Declaration 4.3.3.3. VHDL LIBRARY-USE Declaration 4.3.3.4. HDL Code from Parameterizable Macros Template 4.3.3.5. FIFO Signals 4.3.3.6. FIFO Parameter Settings
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.3.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.3.11. DCFIFO Timing Constraint Setting x
4.3.11.1. Embedded Timing Constraint 4.3.11.2. User Configurable Timing Constraint
4.3.11.2. User Configurable Timing Constraint x
4.3.11.2.1. SDC Commands
4.4. Shift Register (RAM-based) Intel® FPGA IP x
4.4.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP 4.4.2. Shift Register (RAM-based) Intel® FPGA IP Features 4.4.3. Shift Register (RAM-based) Intel® FPGA IP General Description 4.4.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings 4.4.5. Shift Register Ports and Parameters Setting
1. Intel Agilex® 7 Embedded Memory Overview
2. Intel Agilex® 7 Embedded Memory Architecture and Features
3. Intel Agilex® 7 Embedded Memory Design Considerations
4. Intel Agilex® 7 Embedded Memory IP References
5. Intel Agilex® 7 Embedded Memory Debugging
6. Intel Agilex® 7 Embedded Memory User Guide Archives
7. Document Revision History for the Intel Agilex® 7 Embedded Memory User Guide

4.4.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings

Table 57.  Shift Register (RAM-based) Intel® FPGA IP Parameter SettingsThis table lists the parameter for the Shift Register (RAM-based) Intel® FPGA IP.
Configuration Setting Description
How wide should the "shiftin" input and the "shiftout" output buses be? Specify the width of the data input and output buses. This value is represented by the term w in the Shift Register Memory Configuration.
How many taps would you like? Specify the number of taps. This value is represented by the term n in the Shift Register Memory Configuration.
Create groups for each tap output Turn on this option to create separate groups for output data tapped from the register chain. 37
How wide should the distance between taps be? Specify the distance between taps. This value is represented by the term m in the Shift Register Memory Configuration. 38
Create a clock enable port Turn on this option to create an enable signal for register ports. The register ports are always enabled if this option is not turned on. 39
Create an asynchronous clear port Turn on this option to create an asynchronous clear signal. When asserted, the outputs of the shift register are immediately cleared.
Create a synchronous clear port Turn on this option to create a synchronous clear signal. When asserted, the outputs of the shift register are cleared at the next positive clock edge.
What should the RAM block type be? Choose the type of memory block that supports the feature, memory configuration, and capacity for your application. 40
Note:
  1. The widths of the shiftin input bus and shiftout output bus are identical, and they are not registered. However, the output data can be considered synchronous with the clock because the internal read address to the memory block is synchronous to the clock.
  2. The width of the output taps is the multiplication of w (width of input data) and n (number of taps). Also, the word from the MSB of the output taps is equivalent to the shiftout output bus.
37 The combination of these groups represent the taps[wn-1:0] bus.
38 The distance between taps, m, must be at least 3.
39 The registered port is referred to as the internal register at the memory address ports. The shiftin and shiftout ports are not registered.
40 For information about the chosen memory block type, refer to the TriMatrix Embedded Memory Block chapter of your target device handbook. You can also choose AUTO if you are not particular about the RAM block type used. With the AUTO option, the memory block type is determined by the Intel® Quartus® Prime software synthesizer or Fitter at compile time. To determine the type of memory block used, check the Intel® Quartus® Prime Fitter Report.
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