Visible to Intel only — GUID: mhi1464715846022
Ixiasoft
Visible to Intel only — GUID: mhi1464715846022
Ixiasoft
4.2.3. eSRAM Intel Agilex® FPGA IP Parameters
Parameter | Legal Values | Description |
---|---|---|
Interface | ||
Interface
|
On/Off | Specifies the channel to be enabled for eSRAM. There are 4 ports per eSRAM.
|
Parameter | Legal Values | Description |
---|---|---|
Channel Width and Depth | ||
How wide should the data bus be? | — | Specifies the width of the data bus.
|
How many words of memory? | — | Specifies the number of N-bits words for Port. This value is used to derive the number of banks to be turned on. The rest of the banks are shut down for power-saving purpose. Formula for the number of bank(s) enabled is equal to the depth of the port divide by 1024, where 1024 is the depth of each bank.
Note: If you attempt to address a bank that has not been enabled, any resulting data will be random and without value.
|
Port Features | ||
Enable Write Forwarding | On/Off | Enables write forwarding, which ensures data coherency when writing to and reading from the same address in the eSRAM. Write forwarding takes the data present on the write port and forwards it to the read port as read data. Write-forwarded read data requires the same duration of time as a regular read. Read logic does not use data stored in the targeted address, but the data is still written to the address. |