MAX® 10 (Single Supply) FPGA
Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
| Pin Name | Pin Functions | Pin Description | Connection Guidelines |
|---|---|---|---|
| VCC_ONE | Power | Power supply pin for core and periphery through an on-die regulator. The voltage is internally regulated to 1.2 V to supply power to the core and periphery. |
The VCC_ONE power supply pin supports E144, M153, U169, and U324 package-types only. Connect all VCC_ONE pins to either 3.0 V or 3.3 V power supply. Tie VCC_ONE and VCCA with filter using the same power supply on board level. |
| VCCIO[#] | Power | I/O supply voltage pins for banks 1 through 8. Each bank supports different voltage level. The VCCIO pin supplies power to the input and output buffers for banks 1 through 8 for all I/O standards. The VCCIO pin powers up the JTAG and configuration pins. |
Connect these pins to 1.0 V, 1.2 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V power supplies, depending on the I/O standard assigned to each I/O bank.
Note: The 1.0 V VCCIO is not supported on I/O banks 1B and 8. For single-supply device option, the 1.0-V VCCIO is only supported on specific MAX® 10 devices. For the list of supported devices, refer to the Supported I/O Standards section in the MAX® 10 General Purpose I/O User Guide .
If you power-up a device from the power-down state, you need to power the VCCIO for bank 1B (bank 1 for 10M02 devices), bank 8, and the core to the appropriate level for the device to exit POR. The MAX® 10 device enters the configuration stage after exiting the power-up stage with a small POR delay. The VCCIO for bank 1B (bank 1 for 10M02 devices) and bank 8 must be powered up to a voltage between 1.5 V to 3.3 V during configuration. If you are migrating from other MAX® 10 devices to the 10M02 device, the VCCIO1A and VCCIO1B pins are shorted to the VCCIO1 pin of the 10M02 device. If you do not enable the ADC feature, you may connect the VCCIO1A and VCCIO1B pins to different voltage levels, provided that the VREF pin is not used. If the VREF pin is used, you must connect the VCCIO1A and VCCIO1B pins to the same voltage level. If you enable the ADC feature, connect VCCIO1A and VCCIO1B to either 3.0 V or 3.3 V depending on the VCC_ONE pins used. The power supply sharing between the VCCIO1A and VCCIO1B pins requires filtering to isolate the noise. The filter should be located near to the VCCIO1A pins. Only 10M02 devices do not require filtering if VCCIO1A and VCCIO1B share the same power supply. When the ADC feature is enabled, filter is required. If you are migrating from the 10M08 or 10M16 device to the 10M02 device with ADC enabled, replace the filter with 0-Ω resistor in the 10M02 device. For details about the available VCCIO pins for each MAX® 10 device, refer to the respective device pinout file. See Note 4 of the Notes to the MAX® 10 FPGA Pin Connection Guidelines section. Decoupling of these pins depends on the design decoupling requirements of the specific board. |
| VCCA[1..6] | Power | Power supply pins for PLL and ADC block. | Connect these pins to a 3.0 V or 3.3 V power supplies even if the PLL and ADC are not used. These pins must be powered up and powered down at the same time. Connect all VCCA pins together. The VCCA power supply to the FPGA should be isolated for better jitter performance. See Notes 5 and 6 of the Notes to the MAX® 10 FPGA Pin Connection Guidelines section. VCCA[1..4] is available for M153, U169, and U324 packages while VCCA[1..6] is available for the E144 package. For more information about the UFM and CFM power-down requirement, refer to the MAX® 10 User Flash Memory User Guide . |