Clock and PLL Pins
Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
| Pin Name | Pin Functions | Pin Description | Connection Guidelines |
|---|---|---|---|
| CLK [0..7]p | Clock, I/O | Dedicated global clock input pins that can also be used for the positive terminal inputs for differential global clock input or user input pins. When these clock input pins are used as single-ended pins, you can disregard the p notation. The CLK[0..7]p pins can function as regular I/O pins. |
Connect unused pins to the VCCIO of the bank in which the pins reside or GND. See Notes 2 and 3 of the Notes to the MAX® 10 FPGA Pin Connection Guidelines section. |
| CLK[0..7]n | Clock, I/O | Dedicated global clock input pins that can also be used for the negative terminal inputs for differential global clock input or user input pins. When these clock input pins are used as single-ended pins, you can disregard the n notation. The CLK[0..7]n pins can function as regular I/O pins. |
Connect unused pins to the VCCIO of the bank in which the pins reside or GND. See Notes 2 and 3 of the Notes to the MAX® 10 FPGA Pin Connection Guidelines section. |
| DPCLK[0..3] | I/O, Input | The DPCLK pins can connect to the global clock network for high fan-out control signals such as clocks, asynchronous clears, presets, and clock enables. The DPCLK pins cannot feed a PLL input. | Connect unused pins to the VCCIO of the bank they reside in or GND. These pins can function as regular I/O pins. See Note 3 of the Notes to the MAX® 10 FPGA Pin Connection Guidelines section. |
| PLL_[L,R,B,T]_CLKOUTp | I/O, Output | Optional positive terminal for external clock outputs from PLL[1..4]. These pins can be assigned to single-ended or differential I/O standards if it is being fed by a PLL output.
The availability for the PLL_[L,R,B,T]_CLKOUTp pins varies for each device density and package combination. For more details, refer to the specific device pinout file. |
Connect unused pins to GND. These pins can function as regular I/O pins. See Note 3 of the Notes to the MAX® 10 FPGA Pin Connection Guidelines section. |
| PLL_[L,R,B,T]_CLKOUTn | I/O, Output | Optional negative terminal for external clock outputs from PLL[1..4]. These pins can be assigned to single-ended or differential I/O standards if it is being fed by a PLL output.
The availability for the PLL_[L,R,B,T]_CLKOUTn pins varies for each device density and package combination. For more details, refer to the specific device pinout file. |
Connect unused pins to GND. These pins can function as regular I/O pins. See Note 3 of the Notes to the MAX® 10 FPGA Pin Connection Guidelines section. |