MAX® 10 FPGA Device Family Pin Connection Guidelines

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ID 683232
Date 8/20/2024
Public
Document Table of Contents
Document Table of Contents x
MAX® 10 FPGA Device Family Pin Connection Guidelines
MAX® 10 FPGA Device Family Pin Connection Guidelines x
MAX® 10 FPGA Pin Connection Guidelines Power Supply Sharing Guidelines for MAX® 10 FPGA Devices Document Revision History for the MAX® 10 FPGA Device Family Pin Connection Guidelines
MAX® 10 FPGA Pin Connection Guidelines x
Clock and PLL Pins Configuration/JTAG Pins Differential I/O Pins External Memory Interface Pins Reference Pins Analog Input Pins MAX® 10 (Single Supply) FPGA MAX® 10 (Dual Supply) FPGA Notes to the MAX® 10 FPGA Pin Connection Guidelines
Power Supply Sharing Guidelines for MAX® 10 FPGA Devices x
Example 1— MAX® 10 (Dual Supply) FPGA Example 2— MAX® 10 (Dual Supply) FPGA Example 3— MAX® 10 (Dual Supply) FPGA Example 4— MAX® 10 (Single Supply) FPGA Example 5— MAX® 10 (Single Supply) FPGA Example 6— MAX® 10 (Single Supply) FPGA
MAX® 10 FPGA Device Family Pin Connection Guidelines

Example 1— MAX® 10 (Dual Supply) FPGA

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 10.  Power Supply Sharing Guidelines for MAX® 10 (Dual Supply) FPGA – The ADC Feature is Not UsedExample Requiring 3 Power Regulators
Power Pin Name Regulator Group Voltage Level (V) Supply Tolerance Power Source Regulator Sharing Notes
VCC 1 1.2 ±50 mV Switcher 1 Share You have the option to share VCCINT and VCCD_PLL with VCC using proper isolation filters.
VCCINT Isolate
VCCD_PLL Isolate
VCCA 2 2.5 ±5% Switcher1 Share You have the option to share VCCA_ADC with VCCA.
VCCA_ADC
VCCIO 3 Varies ±5% Switcher1 Share Individual power rail.
Note:
  1. Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
  2. Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the MAX® 10 FPGA device is provided in the following figure.
  3. For LPDDR2 interface targeting 200 MHz, you need to constraint the memory device I/O and core power supply to ±3% variation.
  4. Refer to the MAX® 10 FPGA Configuration User Guide for maximum ramp rate requirement.
Figure 1. Example Power Supply Sharing Guidelines for MAX® 10 (Dual Supply) FPGA – The ADC Feature is Not Used
Related Information
1 When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in Note 9 of the Notes to the MAX® 10 FPGA Pin Connection Guidelines.
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