Visible to Intel only — GUID: vgo1448277824364
Ixiasoft
1.4.1. Use Case 1: Source Synchronous I/O Interface
1.4.2. Use Case 2: Driving Data from FPGA through GPIO to External Device
1.4.3. Use Case 3: Multiple-Speed Parallel Interfaces
1.4.4. Use Case 4: GPIO Interface Using 3.0V/2.5V I/O Standard
1.4.5. Use Case 5: Generating Output Clock through GPIO Output Pin
Visible to Intel only — GUID: vgo1448277824364
Ixiasoft
1.4.1. Use Case 1: Source Synchronous I/O Interface
Example 1 shows how you can migrate the source synchronous I/O interface implemented using GPIO to the Altera PHYLite IP core.
Figure 3. Migration of Source Synchronous Output Interface Using GPIO (Output Path) to Altera PHYLite
Figure 4. Migration of Source Synchronous Input Interface Using GPIO (Input Path) to Altera PHYLite