1.3. Performance Comparison
The performance comparison between the Altera GPIO and Altera PHYLite for Parallel Interfaces IP cores measures the setup and hold timing slack window at 200 Mbps.
The comparison between Altera GPIO and Altera PHYLite for Parallel Interfaces IP cores are based on the preliminary timing model in the Quartus Prime software version 15.1, using Arria 10 device (10AX115S2F45I2SGE2). The analysis is done using a simplified design with no user logic in the IP cores.
Note: The timing slack in the following tables do not account for any setup or hold requirements at the receiver or any channel skew between clock and data.
Input/Output | SDR/DDR | Architecture | Clock Network | Worst Setup Slack | Worst Hold Slack | Slack Window (Setup + Hold)1 |
---|---|---|---|---|---|---|
GPIO Input | DDR |
|
Global Clock | 1.093 | 1.177 | 2.270 |
Regional Clock | 1.149 | 1.235 | 2.384 | |||
Periphery Clock | 1.360 | 1.415 | 2.775 | |||
SDR |
|
Global Clock | 1.188 | 1.227 | 2.415 | |
Regional Clock | 1.214 | 1.223 | 2.452 | |||
Periphery Clock | 1.409 | 1.404 | 2.462 | |||
GPIO Output | DDR |
|
Global Clock | 0.023 | 1.831 | 1.854 |
Regional Clock | 0.129 | 1.844 | 1.973 | |||
Periphery Clock | 0.193 | 1.968 | 2.161 | |||
SDR |
|
Global Clock | 0.835 | 1.541 | 2.376 | |
Regional Clock | 0.408 | 1.738 | 2.146 | |||
Periphery Clock | 0.668 | 1.842 | 2.186 |
Input/Output | SDR/DDR | Architecture | Clock Network | Worst Setup Slack | Worst Hold Slack | Slack Window (Setup + Hold) |
---|---|---|---|---|---|---|
Input (1-bit Input) | DDR |
|
PHY clock | 2.054 | 1.995 | 4.049 |
SDR |
|
2.064 | 2.020 | 4.084 | ||
Output (1-bit Input) | DDR |
|
2.197 | 2.216 | 4.413 | |
SDR |
|
2.239 | 2.209 | 4.448 |
In summary, the timing analysis on the source synchronous I/O implementation on the PHYLite IP core provides much larger timing slack window compared to the GPIO IP core. The PHYLite IP core uses the PHY clock network instead of the global clock networks in the core. The change in the clock network enables the PHYLite IP core to achieve better timing performance and avoid core noise effect.
1 Based from multi corner timing analysis.