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1.4.1. Use Case 1: Source Synchronous I/O Interface
1.4.2. Use Case 2: Driving Data from FPGA through GPIO to External Device
1.4.3. Use Case 3: Multiple-Speed Parallel Interfaces
1.4.4. Use Case 4: GPIO Interface Using 3.0V/2.5V I/O Standard
1.4.5. Use Case 5: Generating Output Clock through GPIO Output Pin
Visible to Intel only — GUID: vgo1448256078690
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1.1. Implementing the Altera PHYLite Design
You can generate the Altera PHYLite design using the Intel® Quartus® Prime software, and customize the settings.
To implement your Altera GPIO IP core design to the Altera PHYLite IP core, follow these steps:
- Generate a PHYLite design in the Quartus® Prime software. Customize the design based on the Parameter Settings.
- Connect the modules and the input and output ports, as shown in the following figures.
Figure 1. Input InterfaceFigure 2. Output Interface