AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines

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ID 683231
Date 5/08/2017
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Visible to Intel only — GUID: vgo1449796811476

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Document Table of Contents
Document Table of Contents x
1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines
1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines x
1.1. Implementing the Altera PHYLite Design 1.2. Mapping the Interface Signals 1.3. Performance Comparison 1.4. Use Case Examples 1.5. Altera GPIO to Altera PHYLite Design Example 1.6. Document Revision History
1.1. Implementing the Altera PHYLite Design x
1.1.1. Parameter Settings
1.4. Use Case Examples x
1.4.1. Use Case 1: Source Synchronous I/O Interface 1.4.2. Use Case 2: Driving Data from FPGA through GPIO to External Device 1.4.3. Use Case 3: Multiple-Speed Parallel Interfaces 1.4.4. Use Case 4: GPIO Interface Using 3.0V/2.5V I/O Standard 1.4.5. Use Case 5: Generating Output Clock through GPIO Output Pin
1.5. Altera GPIO to Altera PHYLite Design Example x
1.5.1. Simulation Diagrams 1.5.2. Design Verification
1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines

1.5. Altera GPIO to Altera PHYLite Design Example

You can use the provided design example as a reference to instantiate the Altera PHYLite IP core (input and output in double-data rate mode).

The Altera GPIO to Altera PHYLite design example provides the Altera PHYLite configuration to mimic the GPIO input and output path usage and the expected behavior in simulation and hardware.

The design example consists the following components:
  • Pattern generator (tx_data_output) to generate fixed serial 1100 pattern transmitting through the Altera PHYLite output (ddr_out)
  • Two Altera PHYLite instances configured to mimic the GPIO input and output path usage to transmit and receive source synchronous data respectively.

The reset_n signal connects to the push button switch to control the reset port for the pattern generator and Altera PHYLite input and output instances.

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