Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GX FPGA Data Sheet

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ID 683226
Date 10/26/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. System Compatibility 4. Mechanical Information 5. Thermal Specifications 6. FPGA Interface Manager 7. Board Management Controller 8. PLDM Commands for the Board Management Controller A. Regulatory Information B. References C. Revision History
2. Overview x
2.1. Views of the Intel® PAC with Intel® Arria® 10 GX FPGA 2.2. Overview of Product Features
2.2. Overview of Product Features x
2.2.1. Intel® Arria® 10 GX FPGA 2.2.2. On-Board Memory 2.2.3. Interfaces and Dimensions 2.2.4. Software 2.2.5. Power 2.2.6. CPLD 2.2.7. QSFP+ 2.2.8. Control and Support
2.2.8. Control and Support x
2.2.8.1. PCIe Overview 2.2.8.2. Board Management Controller Overview
4. Mechanical Information x
4.1. Air Duct Disassembly
5. Thermal Specifications x
5.1. Thermal Test Performance Results
6. FPGA Interface Manager x
6.1. Updating the FIM
7. Board Management Controller x
7.1. Features 7.2. Device Peripheral Table 7.3. Updating the BMC Configuration and Firmware
7.1. Features x
7.1.1. BMC Voltage and Thermal Handling
8. PLDM Commands for the Board Management Controller x
8.1. I2C/SMBus Address 8.2. Supported SMBus Commands 8.3. Supported MCTP Commands 8.4. Supported PLDM Commands 8.5. Defined Platform Descriptor Records 8.6. Sensor and Threshold Information
8.3. Supported MCTP Commands x
8.3.1. MCTP Control Messages
8.4. Supported PLDM Commands x
8.4.1. PLDM Base Specification Commands 8.4.2. PLDM for Platform Monitoring and Control Specification Commands
1. Introduction
2. Overview
3. System Compatibility
4. Mechanical Information
5. Thermal Specifications
6. FPGA Interface Manager
7. Board Management Controller
8. PLDM Commands for the Board Management Controller
A. Regulatory Information
B. References
C. Revision History

1. Introduction

Figure 1.  Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

This datasheet for the Intel® PAC with Intel® Arria® 10 GX FPGA shows electrical, mechanical, compliance, and other key specifications. This datasheet assists data center operators and system integrators to properly deploy this PAC into their servers. It also documents the FPGA power envelope, connectivity speeds to memory, and network connectivity, so that accelerator function unit (AFU) developers can properly design and test their IP.

The PAC is supported by the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs. The Intel® Acceleration Stack provides a common developer interface to both application and acceleration function developers and includes drivers, Application Programming Interfaces (APIs) and an FPGA Interface Manager (FIM).

Along with acceleration libraries and development tools, the Acceleration Stack saves development time and enables code re-use across multiple Intel FPGA form-factor products, allowing the developer to focus on the unique value-additon of their solution. Developers can use the Accelerator Functional Unit Developer’s Guide for Intel FPGA Programmable Acceleration Card to get started.

Intel validates each Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA to support large scale deployments requiring FPGA acceleration. This platform is targeted for market-specific acceleration in applications such as:

  • Big Data Analytics
  • Artificial Intelligence
  • Video Transcoding
  • Cyber Security
  • Genomics
  • High-Performance Computing
  • Finance
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