Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GX FPGA Data Sheet

ID 683226
Date 10/26/2020
Public
Document Table of Contents

6. FPGA Interface Manager

The FPGA Interface Manager (FIM) contains the FPGA logic to support the accelerators, including the PCIe IP core, the Core Cache Interface protocol (CCI-P) fabric, the onboard DDR memory interface, and management engine. Specific features of the FIM are listed in the following documents:

The 1024 Mb flash memory stores the FPGA Interface Manager (FIM) which provides a common user interface for placement of accelerator functions. In addition, the FIM allows dynamic downloading of new accelerator functions and updates to the FIM.

The FIM can read all sensor data from the BMC, using the Intel Acceleration Stack. For example, to read the FPGA temperature, use the following command:

sudo fpgainfo temp

To read voltage and current data, use the following command:

sudo fpgainfo power

Refer to the Intel Acceleration Stack Quick Start Guide for the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA to learn how to use these features.