FIR II IP Core: User Guide

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ID 683208
Date 6/12/2020
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Document Table of Contents
Document Table of Contents x
1. About the FIR II IP Core 2. FIR II IP Core Getting Started 3. FIR II IP Core Parameters 4. FIR II IP Core Functional Description 5. Document Revision History for the FIR II IP User Guide A. FIR II IP Core Document Archive
1. About the FIR II IP Core x
1.1. DSP Intel® FPGA IP Features 1.2. FIR II IP Core Features 1.3. FIR II IP Device Support 1.4. DSP Intel® FPGA IP Verification 1.5. FIR II IP Core Release Information 1.6. FIR II IP Core Performance and Resource Utilization
2. FIR II IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the FIR II IP Core Testbench in MATLAB 2.6. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. FIR II IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. FIR II IP Core Parameters x
3.1. FIR II IP Core Filter Specification 3.2. FIR II IP Core Coefficient Settings 3.3. FIR II IP Core Coefficients 3.4. FIR II IP Core Input and Output Options 3.5. FIR II IP Core Implementation Options 3.6. FIR II IP Core Reconfigurability
3.3. FIR II IP Core Coefficients x
3.3.1. Loading Coefficients from a File
3.4. FIR II IP Core Input and Output Options x
3.4.1. Signed Fractional Binary 3.4.2. MSB and LSB Truncation, Saturation, and Rounding
3.5. FIR II IP Core Implementation Options x
3.5.1. Memory and Multiplier Trade-Offs
3.5.1. Memory and Multiplier Trade-Offs x
3.5.1.1. Using Memory Block Threshold 3.5.1.2. Using Dual-port RAM Threshold 3.5.1.3. Using Large RAM Threshold 3.5.1.4. Using Hard Multiplier Threshold
4. FIR II IP Core Functional Description x
4.1. FIR II IP Core Interpolation Filters 4.2. FIR Decimation Filters 4.3. FIR II IP Core Time-Division Multiplexing 4.4. FIR II IP Core Multichannel Operation 4.5. FIR II IP Core Multiple Coefficient Banks 4.6. FIR II IP Core Coefficient Reloading 4.7. Reconfigurable FIR Filters 4.8. FIR II IP Core Interfaces and Signals
4.4. FIR II IP Core Multichannel Operation x
4.4.1. Vectorized Inputs 4.4.2. Channelization 4.4.3. Channel Input and Output Format
4.4.3. Channel Input and Output Format x
4.4.3.1. Eight Channels on Three Wires 4.4.3.2. Four Channels on Four Wires 4.4.3.3. 15 Channels with 15 Valid Cycles and 17 Invalid Cycles 4.4.3.4. 22 Channels with 11 Valid Cycles and 9 Invalid Cycles 4.4.3.5. Super Sample Rate
4.8. FIR II IP Core Interfaces and Signals x
4.8.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.8.2. FIR II IP Core Avalon-ST Interfaces 4.8.3. FIR II IP Core Signals
4.8.2. FIR II IP Core Avalon-ST Interfaces x
4.8.2.1. Avalon-ST Sink Interface 4.8.2.2. Avalon-ST Source Interface
4.8.2.1. Avalon-ST Sink Interface x
4.8.2.1.1. Single Channel on Single Wire 4.8.2.1.2. Multiple Channels on Single Wire 4.8.2.1.3. Multiple Channels on Multiple Wires
1. About the FIR II IP Core
2. FIR II IP Core Getting Started
3. FIR II IP Core Parameters
4. FIR II IP Core Functional Description
5. Document Revision History for the FIR II IP User Guide
A. FIR II IP Core Document Archive

4.8.3. FIR II IP Core Signals

Table 18.  FIR II IP Core Signals with Avalon-ST Interface
Signal Direction Width Description
clk Input 1 Clock signal for all internal FIR II IP core filter registers.
reset_n Input 1 Asynchronous active low reset signal. Resets the FIR II IP core filter control circuit on the rising edge of clk.
coeff_in_clk Input 1 Clock signal for the coefficient reloading mechanism. This clock can have a lower rate than the system clock.
coeff_in_areset Input 1 Asynchronous active high reset signal for the coefficient reloading mechanism.
ast_sink_ready Output 1 FIR filter asserts this signal when can accept data in the current clock cycle. This signal is not available when backpressure is turned off.
ast_sink_valid Input 1 Assert this signal when the input data is valid. When ast_sink_valid is not asserted, the FIR processing stops until you re-assert the ast_sink_valid signal.
ast_sink_data Input (Data width + Bank width) × the number of channel input wires (PhysChanIn)

where,

Bank width= Log2(Number of coefficient sets)

 Sample input data. For a multichannel operation (number of channel input wires > 1), the LSBs of ast_sink_data map to xln_0 of the FIR II IP core filter.

For example:

ast_sink_data[7:0] --> xln_0[7:0]

ast_sink_data[15:8] --> xln_1[7:0]

ast_sink_data[23:16] --> xln_2[7:0]

For multiple coefficient banks, the MSBs of the channel data are mapped to the bank input signal and the LSBs of the channel data map to the data input signal. For reconfigurable FIR filters, the MSBs map to the mode signal.

For example,

Single channel with 4 coefficient banks:

ast_sink_data[9:8] --> BankIn_0

ast_sink_data[7:0] --> xln_0

Multi-channel (4 channels) with 4 coefficient banks:

ast_sink_data[9:8] --> BankIn_0

ast_sink_data[7:0] --> xln_0

ast_sink_data[19:18] --> BankIn_1

ast_sink_data[17:10] --> xln_1

ast_sink_data[29:28] --> BankIn_2

ast_sink_data[27:20] --> xln_2

ast_sink_data[39:38] --> BankIn_3

ast_sink_data[37:30] --> xln_3

ast_sink_sop Input 1 Marks the start of the incoming sample group. The start of packet (SOP) is interpreted as a sample from channel 0.
ast_sink_eop Input 1 Marks the end of the incoming sample group. If data is associated with N channels, the end of packet (EOP) must be driven high when the sample belonging to the last channel (that is, channel N-1), is presented at the data input.
ast_sink_error Input 2 Error signal indicating Avalon-ST protocol violations on the sink side:
  • 00: No error
  • 01: Missing SOP
  • 10: Missing EOP
  • 11: Unexpected EOP

    Other types of errors are also marked as 11.
ast_source_ready Input 1 The downstream module asserts this signal if it is able to accept data. This signal is not available when backpressure is turned off.
ast_source_valid Output 1 The IP core asserts this signal when there is valid data to output.
ast_source_channel Output Log2(number of channels per wire) Indicates the index of the channel whose result is presented at the data output.
ast_source_data Output Data width × number of channel output wires (PhysChanOut) FIR II IP core filter output. For a multichannel operation (number of channel output wires > 1), the least significant bits of ast_source_data are mapped to xOut_0 of the FIR II IP core filter.

For example:

xOut_0[7:0] --> ast_source_data[7:0]

xOut_1[7:0] --> ast_source_data[15:8]

xOut_2[7:0]--> ast_source_data[23:16]

ast_source_sop Output 1 Marks the start of the outgoing FIR II IP core filter result group. If '1', a result corresponding to channel 0 is output.
ast_source_eop Output 1 Marks the end of the outgoing FIR II IP core filter result group. If '1', a result corresponding to channels per wire N-1 is output, where N is the number of channels per wire.
ast_source_error Output 2 Error signal indicating Avalon-ST protocol violations on the source side:
  • 00: No error
  • 01: Missing SOP
  • 10: Missing EOP
  • 11: Unexpected EOP

    Other types of errors are also marked as 11.
coeff_in_address Input Number of coefficients Address input to write new coefficient data.
coeff_in_clk Input - Clock input for coefficients.
coeff_in_areset Input - Reset input for coefficients.
coeff_in_we Input 1 Write enable for memory-mapped coefficients.
coeff_in_data Input Coefficient width Data coefficient input.
coeff_in_read Input Coefficient width Read enable.
coeff_out_valid Output 1 Coefficient read valid signal.
coeff_out_data Output Coefficient width Data coefficient output. The coefficient in memory at the address specified by coeff_in_address.
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