DisplayPort Intel® FPGA IP Release Notes

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Date 4/01/2024
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1. DisplayPort Intel® FPGA IP Release Notes
1. DisplayPort Intel® FPGA IP Release Notes x
1.1. DisplayPort Intel® FPGA IP v20.0.1 1.2. DisplayPort Intel® FPGA IP v20.0.0 1.3. DisplayPort Intel® FPGA IP v19.4.0 1.4. DisplayPort Intel® FPGA IP v19.3.0 1.5. DisplayPort Intel® FPGA IP v19.1 1.6. DisplayPort Intel® FPGA IP v18.1 Update 1 1.7. DisplayPort Intel® FPGA IP v18.1 1.8. DisplayPort Intel® FPGA IP v18.0 1.9. Intel FPGA DisplayPort IP Core v17.1 1.10. DisplayPort IP Core v17.0 1.11. DisplayPort IP Core v16.1 1.12. DisplayPort IP Core v16.0 1.13. DisplayPort IP Core v15.1 1.14. DisplayPort IP Core v15.0 1.15. DisplayPort IP Core v14.1 1.16. DisplayPort Intel® FPGA IP User Guide Archives 1.17. DisplayPort Arria® 10 FPGA IP Design Example User Guide Archives 1.18. DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide Archives 1.19. DisplayPort Stratix® 10 FPGA IP Design Example User Guide Archives
1. DisplayPort Intel® FPGA IP Release Notes

1.8. DisplayPort Intel® FPGA IP v18.0

Table 15.  v18.0 May 2018
Description Impact
Renamed Intel FPGA DisplayPort IP to DisplayPort Intel® FPGA IP as part of standardizing and rebranding exercise. –
Added support for Xcelium* Parallel simulator. These changes are optional. If you do not upgrade your IP core, it does not have these new features.
Added the following files:
  • xcelium_files.tcl
  • xcelium_setup.sh
  • xcelium_sim.sh
Added final support for Cyclone® 10 GX devices. The Cyclone® 10 GX devices are only available in the Quartus® Prime Pro Edition software.
Added new design examples for Cyclone® 10 GX devices in version 17.1.1 release. Refer to the DisplayPort Intel Cyclone 10 GX FPGA IP Design Example User Guide for more information.
Table 16.  Design Files Required for IP Upgrade

The implementation of the IP on hardware requires additional components specific to the device targeted.

These additional components, such as Native PHY, TX PLL, reconfiguration controller, are not included as part of the Quartus® Prime IP Upgrade flow. Upgrading an IP core would require the inclusion of these files generated as part of the IP design example.

Design Example Required Files
Arria® 10
  • quartus\a10_dp_demo.qsf
  • rtl\rx_phy\rx_phy_top.v
  • rtl\tx\tx_phy_top.v
  • rtl\a10_dp_demo.v
  • rtl\bitec_reconfig_alt_a10.v
  • rtl\a10_reconfig_arbiter.sv
  • software\main.c
  • software\rx_utils.c
  • software\tx_utils.c
  • software\tx_utils.h
  • software\config.h
Execute script\build_sw.sh before project compilation to update Software API and regenerate the software .elf file.
Cyclone® 10 GX
  • quartus\c10_dp_demo.qsf
  • rtl\rx_phy\rx_phy_top.v
  • rtl\tx\tx_phy_top.v
  • rtl\c10_dp_demo.v
  • rtl\bitec_reconfig_alt_c10.v
  • rtl\c10_reconfig_arbiter.sv
  • software\main.c
  • software\rx_utils.c
  • software\tx_utils.c
  • software\tx_utils.h
  • software\config.h
Execute script\build_sw.sh before project compilation to update Software API and regenerate the software .elf file.
Related Information
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