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Ixiasoft
1.1. DisplayPort Intel® FPGA IP v20.0.1
1.2. DisplayPort Intel® FPGA IP v20.0.0
1.3. DisplayPort Intel® FPGA IP v19.4.0
1.4. DisplayPort Intel® FPGA IP v19.3.0
1.5. DisplayPort Intel® FPGA IP v19.1
1.6. DisplayPort Intel® FPGA IP v18.1 Update 1
1.7. DisplayPort Intel® FPGA IP v18.1
1.8. DisplayPort Intel® FPGA IP v18.0
1.9. Intel FPGA DisplayPort IP Core v17.1
1.10. DisplayPort IP Core v17.0
1.11. DisplayPort IP Core v16.1
1.12. DisplayPort IP Core v16.0
1.13. DisplayPort IP Core v15.1
1.14. DisplayPort IP Core v15.0
1.15. DisplayPort IP Core v14.1
1.16. DisplayPort Intel® FPGA IP User Guide Archives
1.17. DisplayPort Arria® 10 FPGA IP Design Example User Guide Archives
1.18. DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide Archives
1.19. DisplayPort Stratix® 10 FPGA IP Design Example User Guide Archives
Visible to Intel only — GUID: esn1477287836696
Ixiasoft
1.11. DisplayPort IP Core v16.1
| Description | Impact |
|---|---|
| The 16.1 version of the DisplayPort IP core is available only in Quartus Prime Standard Edition. | These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
| Multi-stream transport (MST) feature does not support audio data channel. |
|
| Added support for multiple TX instances in software API. | |
| Added new Design Example tab in the DisplayPort IP core parameter editor. The design example is for Arria 10 devices. Refer to the DisplayPort IP Core Design Example User Guide for more information. |