DisplayPort Intel® FPGA IP Release Notes

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ID 683194
Date 4/01/2024
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1. DisplayPort Intel® FPGA IP Release Notes
1. DisplayPort Intel® FPGA IP Release Notes x
1.1. DisplayPort Intel® FPGA IP v20.0.1 1.2. DisplayPort Intel® FPGA IP v20.0.0 1.3. DisplayPort Intel® FPGA IP v19.4.0 1.4. DisplayPort Intel® FPGA IP v19.3.0 1.5. DisplayPort Intel® FPGA IP v19.1 1.6. DisplayPort Intel® FPGA IP v18.1 Update 1 1.7. DisplayPort Intel® FPGA IP v18.1 1.8. DisplayPort Intel® FPGA IP v18.0 1.9. Intel FPGA DisplayPort IP Core v17.1 1.10. DisplayPort IP Core v17.0 1.11. DisplayPort IP Core v16.1 1.12. DisplayPort IP Core v16.0 1.13. DisplayPort IP Core v15.1 1.14. DisplayPort IP Core v15.0 1.15. DisplayPort IP Core v14.1 1.16. DisplayPort Intel® FPGA IP User Guide Archives 1.17. DisplayPort Arria® 10 FPGA IP Design Example User Guide Archives 1.18. DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide Archives 1.19. DisplayPort Stratix® 10 FPGA IP Design Example User Guide Archives
1. DisplayPort Intel® FPGA IP Release Notes

1.9. Intel FPGA DisplayPort IP Core v17.1

Table 17.  v17.1 November 2017
Description Impact
Renamed the following as per Intel rebranding:
  • DisplayPort IP core to Intel FPGA DisplayPort IP core
  • Qsys to Platform Designer
–
Added advanced support for Cyclone® 10 GX devices. The Cyclone® 10 GX devices are only available in the Quartus® Prime Pro Edition software.
YCbCr 4:2:0 color format is now supported. These features are only available in the Quartus® Prime Pro Edition software.
The Intel FPGA DisplayPort IP core version 17.1 conforms to Video Electronics Standards Association (VESA) DisplayPort Standard version 1.4.
Added data link rate support for HBR3 (8.10 Gbps). This rate is only available in quad symbols per clock for Arria® 10 and Cyclone® 10 GX devices.
Note: The clock recovery module in the Arria® 10 design examples only support up to 4Kp60 resolution.
Updated the design examples to DisplayPort SST Parallel Loopback With PCR and DisplayPort SST Parallel Loopback Without PCR.

In previous versions of the DisplayPort Intel® FPGA IP design example for Arria® 10 devices, the IOPLL and transceiver PLL output may experience additional jitter. The additional jitter occurs if you source the reference clock from a cascaded PLL output, global clock, or core clock. To compensate for the jitter, the designs require additional constraints. This issue has been fixed in the Quartus® Prime software version 17.1.

If you are upgrading designs that have these additional constraints from the previous versions of Quartus® Prime to version 17.1, you must revise the constraints. Refer to the KDB page for more information.
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