DisplayPort Intel® FPGA IP Release Notes

Download PDF
ID 683194
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Release Notes
1. DisplayPort Intel® FPGA IP Release Notes x
1.1. DisplayPort Intel® FPGA IP v20.0.1 1.2. DisplayPort Intel® FPGA IP v20.0.0 1.3. DisplayPort Intel® FPGA IP v19.4.0 1.4. DisplayPort Intel® FPGA IP v19.3.0 1.5. DisplayPort Intel® FPGA IP v19.1 1.6. DisplayPort Intel® FPGA IP v18.1 Update 1 1.7. DisplayPort Intel® FPGA IP v18.1 1.8. DisplayPort Intel® FPGA IP v18.0 1.9. Intel FPGA DisplayPort IP Core v17.1 1.10. DisplayPort IP Core v17.0 1.11. DisplayPort IP Core v16.1 1.12. DisplayPort IP Core v16.0 1.13. DisplayPort IP Core v15.1 1.14. DisplayPort IP Core v15.0 1.15. DisplayPort IP Core v14.1 1.16. DisplayPort Intel® FPGA IP User Guide Archives 1.17. DisplayPort Arria® 10 FPGA IP Design Example User Guide Archives 1.18. DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide Archives 1.19. DisplayPort Stratix® 10 FPGA IP Design Example User Guide Archives
1. DisplayPort Intel® FPGA IP Release Notes

1.14. DisplayPort IP Core v15.0

Table 22.  v15.0 May 2015
Description Impact
Added preliminary support for Arria 10 devices. These changes are optional. If you do not upgrade your IP core, it does not have these new features.
Updated color support.
  • RGB—18, 24, 30, 36, or 48 bpp
  • YCbCr 4:4:4—24, 30, 36, or 48 bpp
  • YCbCr 4:2:2—16, 20, 24, or 32 bpp
Added source-supported DPCD locations.
Added new bits for DPTX_TEST_80BIT_PATTERN bits.
Removed the Link Quality Generation register bits and combined these bits into the DPTX_TX_CONTROL register.
  • 0000 = Normal video
  • 0001 = Training pattern 1
  • 0010 = Training pattern 2
  • 0011 = Training pattern 3
  • 0111 = Video idle pattern
  • 1001 = D10.2 test pattern (same as training pattern 1)
  • 1010 = Symbol error rate measurement pattern
  • 1011 = PRBS7
  • 1100 = 80-bit custom pattern
  • 1101 = HBR2 compliance test pattern (CP2520 pattern 1)
Added new sink-supported DPCD location bits: TEST_REQUEST, TEST_LINK_RATE, TEST_LANE_COUNT, PHY_TEST_PATTERN, and TEST_80BIT_CUSTOM_PATTERN.
Added simulation testbench for Arria 10 devices.
Related Information
Level Two Title