AN 763: Intel® Arria® 10 SoC Device Design Guidelines

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ID 683192
Date 5/17/2022
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Document Table of Contents
Document Table of Contents x
1. Overview of Design Guidelines for Intel® Arria® 10 SoC FPGAs 2. Guidelines for Interconnecting the Intel® Arria® 10 HPS and FPGA 3. Design Guidelines for HPS Portion of Arria 10 SoC FPGAs 4. Board Design Guidelines for Arria 10 SoC FPGAs 5. Embedded Software Design Guidelines for Arria 10 SoC FPGAs
1. Overview of Design Guidelines for Intel® Arria® 10 SoC FPGAs x
1.1. SoC FPGA Designer's Checklist 1.2. Overview of HPS Design Guidelines for SoC FPGA design 1.3. Overview of Board Design Guidelines for SoC FPGA Design 1.4. Overview of Embedded Software Design Guidelines for SoC FPGA Design 1.5. Overview of Design Guidelines for Intel® Arria® 10 SoC FPGAs Revision History
2. Guidelines for Interconnecting the Intel® Arria® 10 HPS and FPGA x
2.1. Overview of HPS Memory-Mapped Interfaces 2.2. Recommended System Topologies 2.3. Guidelines for Interconnecting the Intel® Arria® 10 HPS and FPGA Revision History
2.1. Overview of HPS Memory-Mapped Interfaces x
2.1.1. HPS-to-FPGA Bridge 2.1.2. Lightweight HPS-to-FPGA Bridge 2.1.3. FPGA-to-HPS Bridge 2.1.4. FPGA-to-SDRAM Ports 2.1.5. Interface Bandwidths
2.2. Recommended System Topologies x
2.2.1. HPS Accesses to FPGA Fabric 2.2.2. Maintaining Cache Coherency 2.2.3. MPU Sharing Data with FPGA 2.2.4. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA
2.2.4. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA x
2.2.4.1. Example 1: FPGA Reading Data from HPS SDRAM Directly 2.2.4.2. Example 2: FPGA Writing Data into HPS SDRAM Directly 2.2.4.3. Example 3: FPGA Reading Cache Coherent Data from HPS 2.2.4.4. Example 4: FPGA Writing Cache Coherent Data to HPS
3. Design Guidelines for HPS Portion of Arria 10 SoC FPGAs x
3.1. Start your SoC FPGA design here 3.2. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory 3.3. HPS Clocking and Reset Design Considerations 3.4. HPS EMIF Design Considerations 3.5. DMA Considerations 3.6. Design Guidelines for HPS Portion of Intel® Arria® 10 SoC FPGAs Revision History
3.1. Start your SoC FPGA design here x
3.1.1. Recommended Starting Point for HPS-to-FPGA Interface Designs 3.1.2. Determining your SoC FPGA Topology
3.2. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory x
3.2.1. HPS Pin Multiplexing Design Considerations 3.2.2. HPS I/O Settings: Constraints and Drive Strengths
3.3. HPS Clocking and Reset Design Considerations x
3.3.1. HPS Clock Planning 3.3.2. Early Pin Planning and I/O Assignment Analysis 3.3.3. Pin Features and Connections for HPS Clocks, Reset and PoR 3.3.4. Internal Clocks 3.3.5. HPS Reset During FPGA Reconfiguration and FPGA Configuration Failures 3.3.6. HPS Peripheral Reset Management
3.4. HPS EMIF Design Considerations x
3.4.1. Considerations for Connecting HPS to SDRAM 3.4.2. HPS SDRAM I/O Locations 3.4.3. Integrating the Arria 10 HPS EMIF with the SoC FPGA Device 3.4.4. HPS Memory Debug
3.4.2. HPS SDRAM I/O Locations x
3.4.2.1. I/O Bank 2K, Lanes 0,1,2 (Addr/Cmd) 3.4.2.2. I/O Bank 2K, Lane 3 (ECC) 3.4.2.3. I/O Bank, 2J (Data) 3.4.2.4. I/O Bank, 2I (Data, 64-, 72-bit interfaces)
3.5. DMA Considerations x
3.5.1. Choosing a DMA Controller 3.5.2. Optimizing DMA Master Bandwidth through HPS Interconnect
4. Board Design Guidelines for Arria 10 SoC FPGAs x
4.1. Power On Board Bring Up and Boot ROM/Boot Loader Debugging 4.2. FPGA Reconfiguration 4.3. HPS Power Design Considerations 4.4. Boundary Scan for HPS 4.5. Design Guidelines for HPS Interfaces 4.6. Connection Guidelines for Unused HPS Block 4.7. Board Design Guidelines for Intel® Arria® 10 SoC FPGAs Revision History
4.2. FPGA Reconfiguration x
4.2.1. Flash Update with HPS Reboot 4.2.2. Partial Reconfiguration of the SoC FPGA
4.3. HPS Power Design Considerations x
4.3.1. Early System and Board Planning 4.3.2. Design Considerations for HPS and FPGA Power Supplies for SoC FPGA devices 4.3.3. Pin Connection Considerations for Board Designs 4.3.4. Power Analysis 4.3.5. Power Optimization
4.3.1. Early System and Board Planning x
4.3.1.1. Early Power Estimation
4.3.1.1. Early Power Estimation x
4.3.1.1.1. Main Worksheet 4.3.1.1.2. IO Worksheet 4.3.1.1.3. IO-IP Worksheet 4.3.1.1.4. HPS Worksheet
4.3.2. Design Considerations for HPS and FPGA Power Supplies for SoC FPGA devices x
4.3.2.1. Consider Device Power Consumption and HPS Performance 4.3.2.2. Consider Desired HPS Boot Clock Frequency
4.3.3. Pin Connection Considerations for Board Designs x
4.3.3.1. Device Power-Up 4.3.3.2. Power Pin Connections and Power Supplies
4.3.5. Power Optimization x
4.3.5.1. Processor and Memory Clock Speeds 4.3.5.2. MPU Standby Modes and Dynamic Clock Gating 4.3.5.3. Managing Peripheral Power 4.3.5.4. Managing Power by Shutting Down Supplies
4.5. Design Guidelines for HPS Interfaces x
4.5.1. HPS EMAC PHY Interfaces 4.5.2. USB Interface Design Guidelines 4.5.3. QSPI Flash Interface Design Guidelines 4.5.4. SD/MMC and eMMC Card Interface Design Guidelines 4.5.5. Provide Flash Memory Reset for QSPI and SD/MMC/eMMC 4.5.6. NAND Flash Interface Design Guidelines 4.5.7. UART Interface Design Guidelines 4.5.8. I2C Interface Design Guidelines
4.5.1. HPS EMAC PHY Interfaces x
4.5.1.1. PHY Interfaces Connected Through Shared I/O 4.5.1.2. PHY Interfaces Connected Through FPGA I/O 4.5.1.3. MDIO 4.5.1.4. Common PHY Interface Design Considerations
4.5.1.1. PHY Interfaces Connected Through Shared I/O x
4.5.1.1.1. RMII 4.5.1.1.2. RGMII
4.5.1.2. PHY Interfaces Connected Through FPGA I/O x
4.5.1.2.1. GMII/MII 4.5.1.2.2. Adapting to RMII 4.5.1.2.3. Adapting to SGMII
4.5.1.4. Common PHY Interface Design Considerations x
4.5.1.4.1. Signal Integrity
5. Embedded Software Design Guidelines for Arria 10 SoC FPGAs x
5.1. Embedded Software for HPS Design Guidelines 5.2. Support and Documentation 5.3. Embedded Software Design Guidelines for Intel® Arria® 10 SoC FPGAs Revision History
5.1. Embedded Software for HPS Design Guidelines x
5.1.1. Purpose 5.1.2. Assembling the components of your Software Development Platform 5.1.3. Selecting an Operating System for your application 5.1.4. Assembling your Software Development Platform for Linux 5.1.5. Assembling your Software Development Platform for a Bare-Metal Application 5.1.6. Assembling your Software Development Platform for Partner OS or RTOS 5.1.7. Choosing Boot Loader Software 5.1.8. Selecting Software Tools for Development, Debug and Trace 5.1.9. Board Bring Up Considerations 5.1.10. Boot and Configuration Design Considerations 5.1.11. Flash Device Driver Design Considerations 5.1.12. HPS ECC Design Considerations 5.1.13. Security Design Considerations 5.1.14. Embedded Software Debugging and Trace
5.1.2. Assembling the components of your Software Development Platform x
5.1.2.1. Golden Hardware Reference Design (GHRD)
5.1.3. Selecting an Operating System for your application x
5.1.3.1. Using Linux or RTOS 5.1.3.2. Developing a Bare-Metal Application 5.1.3.3. Using the Bootloader as a Bare-Metal Framework 5.1.3.4. Using Symmetrical vs. Asymmetrical Multiprocessing (SMP vs. AMP) Modes
5.1.4. Assembling your Software Development Platform for Linux x
5.1.4.1. Golden System Reference Design (GSRD) for Linux 5.1.4.2. GSRD for Linux Build Flow 5.1.4.3. Source Code Management Considerations 5.1.4.4. Linux Device Tree Design Considerations
5.1.8. Selecting Software Tools for Development, Debug and Trace x
5.1.8.1. Selecting Software Build Tools 5.1.8.2. Selecting Software Debug Tools 5.1.8.3. Selecting Software Trace Tools
5.1.9. Board Bring Up Considerations x
5.1.9.1. Plan the SDRAM Initialization
5.1.10. Boot and Configuration Design Considerations x
5.1.10.1. Boot Design Considerations 5.1.10.2. Configuration
5.1.10.1. Boot Design Considerations x
5.1.10.1.1. Boot Source 5.1.10.1.2. Select Desired Flash Device 5.1.10.1.3. BSEL Options 5.1.10.1.4. Boot Clock 5.1.10.1.5. Determine Boot Fuses Usage 5.1.10.1.6. CSEL Options 5.1.10.1.7. Determine Flash Programming Method 5.1.10.1.8. Selecting NAND Flash Devices 5.1.10.1.9. Selecting QSPI Flash Devices 5.1.10.1.10. Reference Materials
5.1.10.2. Configuration x
5.1.10.2.1. Traditional Configuration 5.1.10.2.2. HPS-Initiated Configuration
5.1.12. HPS ECC Design Considerations x
5.1.12.1. General ECC Design Considerations 5.1.12.2. ECC for External SDRAM Interface 5.1.12.3. ECC for L2 Cache Data Memory 5.1.12.4. ECC for Flash Memory
5.2. Support and Documentation x
5.2.1. Support 5.2.2. Hardware Documentation 5.2.3. Software Documentation
5.2.3. Software Documentation x
5.2.3.1. Example of Prebuilt Bootloaders for the Intel® Arria® 10 SoC Development Kit
1. Overview of Design Guidelines for Intel® Arria® 10 SoC FPGAs
2. Guidelines for Interconnecting the Intel® Arria® 10 HPS and FPGA
3. Design Guidelines for HPS Portion of Arria 10 SoC FPGAs
4. Board Design Guidelines for Arria 10 SoC FPGAs
5. Embedded Software Design Guidelines for Arria 10 SoC FPGAs

5.2.3.1. Example of Prebuilt Bootloaders for the Intel® Arria® 10 SoC Development Kit

If you are using the Intel® Arria® 10 Development Kit, there are existing prebuilt U-boot and UEFI bootloaders that you can use to test your design. These prebuilt bootloaders work with different HPS boot flash, and assigns the HPS Dedicated and Shared I/O according to the following layout:

Table 13.  HPS Dedicated I/O
HPS Dedicated I/O Boot from SDMMC Boot from QSPI Boot from NAND
4 sdmmc.data0 qspi.clk nand.adq0
5 sdmmc.cmd qspi.io0 nand.adq1
6 sdmmc.cclk qspi.ss0 nand.we_n
7 sdmmc.data1 qspi.io1 nand.re_n
8 sdmmc.data2 qspi.io2_wpn nand.adq2
9 sdmmc.data3 qspi.io3_hold nand.adq3
10 nand.cle
11 nand.ale
12 sdmmc.data4 nand.rb
13 sdmmc.data5 nand.ce_n
14 sdmmc.data6 nand.adq4
15 sdmmc.data7 nand.adq5
16 uart1.tx uart1.tx nand.adq6
17 uart1.rx uart1.rx nand.adq7
Table 14.  HPS Shared I/O
HPS Shared I/O Boot from SDMMC Boot from QSPI Boot from NAND
Q1_1 usb0.clk usb0.clk usb0.clk
Q1_2 usb0.stp usb0.stp usb0.stp
Q1_3 usb0.dir usb0.dir usb0.dir
Q1_4 usb0.data0 usb0.data0 usb0.data0
Q1_5 usb0.data1 usb0.data1 usb0.data1
Q1_6 usb0.nxt usb0.nxt usb0.nxt
Q1_7 usb0.data2 usb0.data2 usb0.data2
Q1_8 usb0.data3 usb0.data3 usb0.data3
Q1_9 usb0.data4 usb0.data4 usb0.data4
Q1_10 usb0.data5 usb0.data5 usb0.data5
Q1_11 usb0.data6 usb0.data6 usb0.data6
Q1_12 usb0.data7 usb0.data7 usb0.data7
Q2_1 emac0.tx_clk emac0.tx_clk emac0.tx_clk
Q2_2 emac0.tx_ctl emac0.tx_ctl emac0.tx_ctl
Q2_3 emac0.rx_clk emac0.rx_clk emac0.rx_clk
Q2_4 emac0.rx_ctl emac0.rx_ctl emac0.rx_ctl
Q2_5 emac0.txd0 emac0.txd0 emac0.txd0
Q2_6 emac0.txd1 emac0.txd1 emac0.txd1
Q2_7 emac0.rxd0 emac0.rxd0 emac0.rxd0
Q2_8 emac0.rxd1 emac0.rxd1 emac0.rxd1
Q2_9 emac0.txd2 emac0.txd2 emac0.txd2
Q2_10 emac0.txd3 emac0.txd3 emac0.txd3
Q2_11 emac0.rxd2 emac0.rxd2 emac0.rxd2
Q2_12 emac0.rxd3 emac0.rxd3 emac0.rxd3
Q3_1 spim1.clk spim1.clk spim1.clk
Q3_2 spim1.mosi spim1.mosi spim1.mosi
Q3_3 spim1.miso spim1.miso spim1.miso
Q3_4 spim1.ss0_n spim1.ss0_n spim1.ss0_n
Q3_5 spim1.ss1_n spim1.ss1_n spim1.ss1_n
Q3_6 gpio1.io5 gpio1.io5 gpio1.io5
Q3_7 uart1.tx
Q3_8 uart1.rx
Q3_9
Q3_10
Q3_11 emac0.mdio emac0.mdio emac0.mdio
Q3_12 emac0.mdc emac0.mdc emac0.mdc
Q4_1 i2c1.sda i2c1.sda i2c1.sda
Q4_2 i2c1.scl i2c1.scl i2c1.scl
Q4_3 gpio1.io14 gpio1.io14 gpio1.io14
Q4_4 trace.clk trace.clk trace.clk
Q4_5 gpio1.io16 gpio1.io16 gpio1.io16
Q4_6 gpio1.io17 gpio1.io17 gpio1.io17
Q4_7
Q4_8
Q4_9 trace.d0 trace.d0 trace.d0
Q4_10 trace.d1 trace.d1 trace.d1
Q4_11 trace.d2 trace.d2 trace.d2
Q4_12 trace.d3 trace.d3 trace.d3
Select the prebuilt bootloaders, you want to use to test your design.
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