AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Public
Document Table of Contents

2.2.4.3. Example 3: FPGA Reading Cache Coherent Data from HPS

In this example, the FPGA requires access to data originating in the HPS. The MPU in the HPS recently accessed this data so there is a chance that the data is still contained in the cache and therefore it may be optimal for the FPGA to access the cached data. To avoid the overhead of software having to flush dirty cache lines, the FPGA can perform cache coherent reads to the FPGA-to-HPS bridge. It is important that the buffers being read be relatively small in size. Otherwise, the L2 cache might thrash reading data from SDRAM for the majority of the transfer. For large buffer transfers it is more appropriate to have the FPGA read data from the FPGA-to-SDRAM ports directly as shown in Example 1.

GUIDELINE: Perform full accesses targeting FPGA-to-HPS bridge.

For the transaction to be cacheable, the FPGA master must read from the FPGA-to-HPS bridge and at a minimum set the cacheable and read-allocate bits of the ARCACHE signal. If you use Avalon-MM masters to access cacheable data, you must provide logic to force the ARCACHE signal to the appropriate values. An example of forcing Avalon-MM transactions to be cacheable can be found in the FPGA-to-HPS Bridge design example.

Figure 5. FPGA Reading Cache Coherent DataFor abbreviations, refer to the figure in Overview of HPS Memory-Mapped Interfaces.

GUIDELINE: Perform cacheable accesses aligned to 32 bytes targeting the FPGA-to-HPS bridge.

The ACP slave of the HPS is optimized for transactions that are the same size as the cache line (32 bytes). As a result, you should attempt to align the data to 32-byte boundaries and ensure after data width adaptation the burst length into the 64-bit ACP slave is four beats long. For example, if the FPGA-to-HPS bridge is set up for 128-bit transactions you should align the data to be 32-byte aligned and perform full 128-bit accesses with a burst length of 2.

GUIDELINE: Access 32 bytes per cacheable transaction.

Ensure that each burst transaction accesses 32 bytes. Each transaction must start on a 32-byte boundary.

Table 6.  Burst Lengths for 32-Byte Alignment
Bridge Width (Bits) Access Size (Bytes) Burst Length
32 4 8
64 8 4
128 16 2