AN 710: Altera JESD204B MegaCore Function and ADI AD9680 Hardware Checkout Report

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Date 5/11/2015
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Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup for Stratix V Advanced Systems Development Kit 1.3. Hardware Setup for Arria 10 FPGA Development Kit 1.4. Hardware Checkout Methodology 1.5. JESD204B IP Core and ADC Configurations 1.6. Test Results for Stratix V and Arria 10 FPGA 1.7. Test Result Comments 1.8. AN 710 Document Revision History
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Descrambling 1.4.4. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Code Group Synchronization (CGS) 1.4.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report

1.6. Test Results for Stratix V and Arria 10 FPGA

Table 7.  Results Definition

Result

Definition

PASS

The Device Under Test (DUT) was observed to exhibit conformant behavior.

PASS with comments

The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included, such as due to time limitations only a portion of the testing was performed.

FAIL

The DUT was observed to exhibit non-conformant behavior.

Warning

The DUT was observed to exhibit behavior that is not recommended.

Refer to comments

From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included.

The following table lists the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 8.  Test Results

Test

L

M

F

Subclass

SCR

K

Data rate (Mbps)

Sampling Clock (MHz)

Link Clock (MHz)

Result

1

1

1

2

1

0

16

12500

625

312.5

Pass

2

1

1

2

1

1

16

12500

625

312.5

Pass

3

1

1

2

1

0

32

12500

625

312.5

Pass

4

1

1

2

1

1

32

12500

625

312.5

Pass

5

2

1

1

1

0

20

12500

1250

312.5

Pass

6

2

1

1

1

1

20

12500

1250

312.5

Pass

7

2

1

1

1

0

32

12500

1250

312.5

Pass

8

2

1

1

1

1

32

12500

1250

312.5

Pass

9

2

1

2

1

0

16

12500

1250

312.5

Pass

10

2

1

2

1

1

16

12500

1250

312.5

Pass

11

2

1

2

1

0

32

12500

1250

312.5

Pass

12

2

1

2

1

1

32

12500

1250

312.5

Pass

13

4

1

1

1

0

20

6250

1250

156.25

Pass

14

4

1

1

1

1

20

6250

1250

156.25

Pass

15

4

1

1

1

0

32

6250

1250

156.25

Pass

16

4

1

1

1

1

32

6250

1250

156.25

Pass

17

4

1

2

1

0

16

6250

1250

156.25

Pass

18

4

1

2

1

1

16

6250

1250

156.25

Pass

19

4

1

2

1

0

32

6250

1250

156.25

Pass

20

4

1

2

1

1

32

6250

1250

156.25

Pass

21

1

2

4

1

0

16

12500

312.5

312.5

Pass

22

1

2

4

1

1

16

12500

312.5

312.5

Pass

23

1

2

4

1

0

32

12500

312.5

312.5

Pass

24

1

2

4

1

1

32

12500

312.5

312.5

Pass

25

2

2

2

1

0

16

12500

625

312.5

Pass

26

2

2

2

1

1

16

12500

625

312.5

Pass

27

2

2

2

1

0

32

12500

625

312.5

Pass

28

2

2

2

1

1

32

12500

625

312.5

Pass

29

4

2

1

1

0

20

12500

1250

312.5

Pass

30

4

2

1

1

1

20

12500

1250

312.5

Pass

31

4

2

1

1

0

32

12500

1250

312.5

Pass

32

4

2

1

1

1

32

12500

1250

312.5

Pass

33

4

2

2

1

0

16

12500

1250

312.5

Pass

34

4

2

2

1

1

16

12500

1250

312.5

Pass

35

4

2

2

1

0

32

12500

1250

312.5

Pass

36

4

2

2

1

1

32

12500

1250

312.5

Pass

The following table shows the Stratix V FPGA results for test cases DL.1, DL.2, and DL.3 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 9.  Test Results For Deterministic Latency Measurement (Stratix V)

Test

L

M

F

Subclass

K

Data rate (Mbps)

Sampling Clock (MHz)

Link Clock (MHz)

Result

DL.1

1

1

2

1

32

12500

625

312.5

Pass

DL.2

1

1

2

1

32

12500

625

312.5

Pass

DL.3

1

1

2

1

32

12500

625

312.5

Pass with comments.

Link clock observed = 115–116 with ADC LMFC offset register set to 0x00

DL.1

2

1

1

1

32

12500

1250

312.5

Pass

DL.2

2

1

1

1

32

12500

1250

312.5

Pass

DL.3

2

1

1

1

32

12500

1250

312.5

Pass with comments.

Link clock observed = 75 with ADC LMFC offset register set to 0x00

DL.1

2

1

2

1

32

12500

1250

312.5

Pass

DL.2

2

1

2

1

32

12500

1250

312.5

Pass

DL.3

2

1

2

1

32

12500

1250

312.5

Pass with comments.

Link clock observed = 115 with ADC LMFC offset register set to 0x0C

DL.1

4

1

1

1

32

6250

1250

156.25

Pass

DL.2

4

1

1

1

32

6250

1250

156.25

Pass

DL.3

4

1

1

1

32

6250

1250

156.25

Pass with comments.

Link clock observed = 67 with ADC LMFC offset register set to 0x00

DL.1

4

1

2

1

32

6250

1250

156.25

Pass

DL.2

4

1

2

1

32

6250

1250

156.25

Pass

DL.3

4

1

2

1

32

6250

1250

156.25

Pass with comments.

Link clock observed = 115–116 with ADC LMFC offset register set to 0x08

DL.1

1

2

4

1

32

12500

312.5

312.5

Pass

DL.2

1

2

4

1

32

12500

312.5

312.5

Pass

DL.3

1

2

4

1

32

12500

312.5

312.5

Pass with comments.

Link clock observed = 195 with ADC LMFC offset register set to 0x00

DL.1

2

2

2

1

32

12500

625

312.5

Pass

DL.2

2

2

2

1

32

12500

625

312.5

Pass

DL.3

2

2

2

1

32

12500

625

312.5

Pass with comments.

Link clock observed = 115–116 with ADC LMFC offset register set to 0x00

DL.1

4

2

1

1

32

12500

1250

312.5

Pass

DL.2

4

2

1

1

32

12500

1250

312.5

Pass

DL.3

4

2

1

1

32

12500

1250

312.5

Pass with comments.

Link clock observed = 75 with ADC LMFC offset register set to 0x14

DL.1

4

2

2

1

32

12500

1250

312.5

Pass

DL.2

4

2

2

1

32

12500

1250

312.5

Pass

DL.3

4

2

2

1

32

12500

1250

312.5

Pass with comments.

Link clock observed = 115 with ADC LMFC offset register set to 0x10

The following table shows the Arria 10 FPGA results for test cases DL.1, DL.2, and DL.3 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 10.  Test Results For Deterministic Latency Measurement (Arria 10)
Test L M F Subclass K Data rate (Gbps) Sampling Clock (MHz) Link Clock (MHz) Result
DL.1 1 1 2 1 32 12.5 625 312.5 PASS
DL.2 1 1 2 1 32 12.5 625 312.5 PASS
DL.3 1 1 2 1 32 12.5 625 312.5

PASS with comments.

Link clock observed = 115 with ADC LMFC offset register set to 0x00.

DL.1 1 2 4 1 32 12.5 312.5 312.5 PASS
DL.2 1 2 4 1 32 12.5 312.5 312.5 PASS
DL.3 1 2 4 1 32 12.5 312.5 312.5

PASS with comments.

Link clock observed = 195 with ADC LMFC offset register set to 0x00.

DL.1 2 1 1 1 32 12.5 1250 312.5 PASS
DL.2 2 1 1 1 32 12.5 1250 312.5 PASS
DL.3 2 1 1 1 32 12.5 1250 312.5

PASS with comments.

Link clock observed = 67 with ADC LMFC offset register set to 0x00.

DL.1 2 1 2 1 32 12.5 1250 312.5 PASS
DL.2 2 1 2 1 32 12.5 1250 312.5 PASS
DL.3 2 1 2 1 32 12.5 1250 312.5

PASS with comments.

Link clock observed = 99 with ADC LMFC offset register set to 0x00.

DL.1 2 2 2 1 32 12.5 625 312.5 PASS
DL.2 2 2 2 1 32 12.5 625 312.5 PASS
DL.3 2 2 2 1 32 12.5 625 312.5

PASS with comments.

Link clock observed = 115 with ADC LMFC offset register set to 0x00.

DL.1 4 1 1 1 32 6.25 1250 156.25 PASS
DL.2 4 1 1 1 32 6.25 1250 156.25 PASS
DL.3 4 1 1 1 32 6.25 1250 156.25

PASS with comments.

Link clock observed = 67 with ADC LMFC offset register set to 0x00.

DL.4 4 1 1 1 32 6.25 1250 156.25 PASS
DL.1 4 1 2 1 32 6.25 1250 156.25 PASS
DL.2 4 1 2 1 32 6.25 1250 156.25 PASS
DL.3 4 1 2 1 32 6.25 1250 156.25

PASS with comments.

Link clock observed = 99 with ADC LMFC offset register set to 0x00.

DL.1 4 2 1 1 32 12.5 1250 312.5 PASS
DL.2 4 2 1 1 32 12.5 1250 312.5 PASS
DL.3 4 2 1 1 32 12.5 1250 312.5

PASS with comments.

Link clock observed = 67 with ADC LMFC offset register set to 0x00.

DL.1 4 2 2 1 32 12.5 1250 312.5 PASS
DL.2 4 2 2 1 32 12.5 1250 312.5 PASS
DL.3 4 2 2 1 32 12.5 1250 312.5

PASS with comments.

Link clock observed = 99 with ADC LMFC offset register set to 0x00.

The following figure shows the SignalTap II waveform of the clock count from the deassertion of SYNC~ to the assertion of jesd204_rx_link_valid signal, the first output of the ramp test pattern (DL.3 test case). The clock count measures the first user data output latency.

Figure 9.  Deterministic Latency Measurement Ramp Test Pattern Diagram



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