AN 710: Altera JESD204B MegaCore Function and ADI AD9680 Hardware Checkout Report

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ID 683170
Date 5/11/2015
Public
Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup for Stratix V Advanced Systems Development Kit 1.3. Hardware Setup for Arria 10 FPGA Development Kit 1.4. Hardware Checkout Methodology 1.5. JESD204B IP Core and ADC Configurations 1.6. Test Results for Stratix V and Arria 10 FPGA 1.7. Test Result Comments 1.8. AN 710 Document Revision History
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Descrambling 1.4.4. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Code Group Synchronization (CGS) 1.4.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report

1.5. JESD204B IP Core and ADC Configurations

The JESD204B IP core parameters (L, M and F) in this hardware checkout are natively supported by the AD9680 device's quick configuration register at address 0x570. The transceiver data rate, sampling clock frequency, and other JESD204B IP core parameters comply with the AD9680 operating conditions.

The hardware checkout testing implements the JESD204B IP core with the following parameter configuration.

Table 6.  Parameter Configuration

Configuration

Setting

LMF

112

124

211

212

222

411

412

421

422

HD

0

0

1

0

0

1

0

1

0

S

1

1

1

2

1

2

4

1

2

N

14

14

14

14

14

14

14

14

14

N’

16

16

16

16

16

16

16

16

16

CS

0

0

0

0

0

0

0

0

0

CF

0

0

0

0

0

0

0

0

0

ADC Device Clock (MHz)

625

312.5

1250

1250

625

1250

1250

1250

1250

ADC Sampling Clock (MHz)

625

312.5

1250

1250

625

1250

1250

1250

1250

FPGA Device Clock (MHz) 6

312.5

312.5

312.5

312.5

312.5

156.25

312.5

312.5

312.5

FPGA Management Clock (MHz)

100

100

100

100

100

100

100

100

100

FPGA Frame Clock (MHz) 7

312.5

312.5

312.5

312.5

312.5

156.25

312.5 or 156.25 (For Arria 10)

312.5

312.5

FPGA Link Clock (MHz) 7

312.5

312.5

312.5

312.5

312.5

156.25

156.25

312.5

312.5

Lane Rate (Gbps)

12.5

12.5

12.5

12.5

12.5

6.25

6.25

12.5

12.5

Character Replacement

Enabled

Enabled

Enabled

Enabled

Enabled

Enabled

Enabled

Enabled

Enabled

Data Pattern

PRBS-9 Ramp8

PRBS-9 Ramp8

PRBS-9 Ramp8

PRBS-9 Ramp8

PRBS-9 Ramp8

PRBS-9 Ramp8

PRBS-9 Ramp8

PRBS-9 Ramp8

PRBS-9 Ramp8

6 The device clock is used to clock the transceiver.
7 The frame clock and link clock is derived from the device clock using an internal PLL.
8 The ramp pattern is used in deterministic latency measurement test cases DL.1, DL.2, and DL.3only.
Level Two Title