AN 710: Altera JESD204B MegaCore Function and ADI AD9680 Hardware Checkout Report

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ID 683170
Date 5/11/2015
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Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup for Stratix V Advanced Systems Development Kit 1.3. Hardware Setup for Arria 10 FPGA Development Kit 1.4. Hardware Checkout Methodology 1.5. JESD204B IP Core and ADC Configurations 1.6. Test Results for Stratix V and Arria 10 FPGA 1.7. Test Result Comments 1.8. AN 710 Document Revision History
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Descrambling 1.4.4. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Code Group Synchronization (CGS) 1.4.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report

1.1. Hardware Requirements

The hardware checkout test requires the following hardware and software tools:

  • Stratix V Advanced Systems Development Kit with 15 V power adaptor
  • Arria 10 FPGA Development Kit
  • ADI AD9680 EVM with 4.5 V power adaptor 1
  • Mini-USB cable
  • Clock source card capable of generating configurable device clock frequencies
Related Information
1 The power adaptor is not needed for the production version of AD9680-1000EBZ EVM (as shown in Figure 3).
2 The AD9680 EVM used in this report differs from the production version of AD9680-1000EBZ EVM. However, there is no difference in terms of functionality between these two EVM.
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