AN 710: Altera JESD204B MegaCore Function and ADI AD9680 Hardware Checkout Report

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ID 683170
Date 5/11/2015
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Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup for Stratix V Advanced Systems Development Kit 1.3. Hardware Setup for Arria 10 FPGA Development Kit 1.4. Hardware Checkout Methodology 1.5. JESD204B IP Core and ADC Configurations 1.6. Test Results for Stratix V and Arria 10 FPGA 1.7. Test Result Comments 1.8. AN 710 Document Revision History
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Descrambling 1.4.4. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Code Group Synchronization (CGS) 1.4.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report

1.4.3. Descrambling

The PRBS checker at the RX transport layer checks the data integrity of descrambler.

The SignalTap II Logic Analyzer tool monitors the operation of the RX transport layer.

Table 4.  Descrambler Test Cases

Test Case

Objective

Description

Passing Criteria

SCR.1

Check the functionality of the descrambler using PRBS-9 test pattern.

Enable scrambler at the ADC and descrambler at the RX JESD204B IP core.

The signals that are tapped in this test case are similar to test case TL.1

  • The jesd204_rx_data_valid signal is asserted.
  • The data_error and jesd204_rx_int signals are deasserted.
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