1.4.4. Deterministic Latency (Subclass 1)
Figure below shows the block diagram of deterministic latency test setup. A SYSREF generator provides a periodic SYSREF pulse for both the AD9680 and JESD204B IP core. The SYSREF generator is running in link clock domain and the period of SYSREF pulse is configured to the desired multiframe size. The SYSREF pulse restarts the LMF counter and realigns it to the LMFC boundary.
Figure 6. Deterministic Latency Test Setup Block Diagram for Stratix V FPGA
Figure 7. Deterministic Latency Test Setup Block Diagram for Arria 10 FPGA
Figure 8. Deterministic Latency Measurement Timing Diagram
With the setup above, three test cases are defined to prove deterministic latency. The continuous SYSREF detection mode is enabled on the JESD204B IP core and AD9680 for this deterministic measurement.
| Test Case |
Objective |
Description |
Passing Criteria |
|---|---|---|---|
| DL.1 |
Check the FPGA SYSREF single detection. |
Check that the FPGA detects the first rising edge of SYSREF pulse. Read the status of sysref_singledet (bit[2]) identifier in the syncn_sysref_ctrl register at address 0x54. |
The value of sysref_singledet identifier should be zero. |
| DL.2 |
Check the SYSREF capture. |
Check that the FPGA and ADC capture SYSREF correctly and restart the LMF counter. Both the FPGA and ADC are also reset repetitively. Read the value of rbd_count (bit[10:3]) identifier in rx_status0 register at address 0x80. |
If the SYSREF is captured correctly and the LMF counter restarts, for every reset, the rbd_count value should only vary by two integers due to word alignment. |
| DL.3 |
Check the latency from start of SYNC~ deassertion to first user data output. |
Check that the latency is fixed for every FPGA reset and power cycle. Record the number of link clocks from the start of SYNC~ deassertion to the first user data output, which is the assertion of jesd204_rx_link_valid signal. |
Consistent latency from the start of SYNC~ deassertion to the assertion of jesd204_rx_link_valid. signal. |