External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide

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ID 683162
Date 6/21/2021
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ FPGA IP 3. Design Example Description for External Memory Interfaces Intel® Agilex™ FPGA IP 4. External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide Archives 5. Document Revision History for External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Generating the Synthesizable EMIF Design Example 2.4. Generating the EMIF Design Example for Simulation 2.5. Simulation Versus Hardware Implementation 2.6. Simulating External Memory Interface IP With ModelSim 2.7. Pin Placement for Intel® Agilex™ EMIF IP 2.8. Compiling and Programming the Intel® Agilex™ EMIF Design Example 2.9. Generating a Design Example with the Calibration Debug Option 2.10. Generating a Design Example with the TG Configuration Option 2.11. Using the Design Example with the EMIF Debug Toolkit
2.2. Generating and Configuring the EMIF IP x
2.2.1. Intel® Agilex™ EMIF Parameter Editor Guidelines
2.10. Generating a Design Example with the TG Configuration Option x
2.10.1. Enabling the Traffic Generator in a Design Example
3. Design Example Description for External Memory Interfaces Intel® Agilex™ FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Designs Interface Tab
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ FPGA IP
3. Design Example Description for External Memory Interfaces Intel® Agilex™ FPGA IP
4. External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide Archives
5. Document Revision History for External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide

2.3. Generating the Synthesizable EMIF Design Example

For the Intel® Agilex™ development kit, it is sufficient to leave most of the Intel® Agilex™ EMIF IP settings at their default values. To generate the synthesizable design example, follow these steps:
  1. On the Example Designs tab, ensure that the Synthesis box is checked.
    • If you are implementing single interface example design, configure the EMIF IP and click File➤ Save to save the current setting into the user IP variation file (<user instance name>.ip).
      Figure 2. 
    • If you are implementing an example design with multiple interfaces, specify Number of IPs to the desired number of interfaces. You can see the total number of EMIF ID same as the selected Number of IPs. Follow these steps to configure each interface:
      1. Select the Cal-IP to specify the connection of the interface to the Calibration IP.
      2. Configure the EMIF IP accordingly in all the Parameter Editor Tab.
      3. Return to Example Design tab and click Capture on the desired EMIF ID.
      4. Repeat step a to c for all EMIF ID.
      5. You may click the Clear button to remove the captured parameters and repeat step a to c to make changes to the EMIF IP.
      6. Click File➤ Save to save the current setting into the user IP variation file (<user instance name>.ip).
        Figure 3. 

  2. Click Generate Example Design in the upper-right corner of the window.
  3. Specify a directory for the EMIF design example and click OK. Successful generation of the EMIF design example creates the following fileset under a qii directory.
  4. Click File > Exit to exit the IP Parameter Editor Pro window. The system prompts, Recent changes have not been generated. Generate now? Click No to continue with the next flow.
  5. To open the example design, click File > Open Project, and navigate to the <project_directory>/<design_example_name>/qii/ed_synth.qpf and click Open.
    Note: For information on compiling and programming the design example, refer to Compiling and Programming the Intel® Agilex™ EMIF Design Example.
    Figure 4. Generated Synthesizable Design Example File Structure

For information on constructing a system with two or more external memory interfaces, refer to Creating a Design Example with Multiple EMIF Interfaces, in the External Memory Interfaces Intel® Agilex™ FPGA IP User Guide.

For information on debugging multiple interfaces, refer to Enabling the EMIF Toolkit in an Existing Design, in the External Memory Interfaces Intel® Agilex™ FPGA IP User Guide.

Note:

If you don't select the Simulation or Synthesis checkbox, the destination directory contains only Platform Designer design files, which are not compilable by the Intel® Quartus® Prime software directly, but which you can view or edit in the Platform Designer. In this situation you can run the following commands to generate synthesis and simulation file sets.

  • To create a compilable project, you must run the 
    quartus_sh -t make_qii_design.tcl
    script in the destination directory.
  • To create a simulation project, you must run the 
    quartus_sh -t make_sim_design.tcl
    script in the destination directory.
Note: If you have generated a design example and then make changes to it in the parameter editor, you must regenerate the design example to see your changes implemented. The newly generated design example does not overwrite the existing design example files.
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