External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide

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ID 683162
Date 6/21/2021
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ FPGA IP 3. Design Example Description for External Memory Interfaces Intel® Agilex™ FPGA IP 4. External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide Archives 5. Document Revision History for External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Generating the Synthesizable EMIF Design Example 2.4. Generating the EMIF Design Example for Simulation 2.5. Simulation Versus Hardware Implementation 2.6. Simulating External Memory Interface IP With ModelSim 2.7. Pin Placement for Intel® Agilex™ EMIF IP 2.8. Compiling and Programming the Intel® Agilex™ EMIF Design Example 2.9. Generating a Design Example with the Calibration Debug Option 2.10. Generating a Design Example with the TG Configuration Option 2.11. Using the Design Example with the EMIF Debug Toolkit
2.2. Generating and Configuring the EMIF IP x
2.2.1. Intel® Agilex™ EMIF Parameter Editor Guidelines
2.10. Generating a Design Example with the TG Configuration Option x
2.10.1. Enabling the Traffic Generator in a Design Example
3. Design Example Description for External Memory Interfaces Intel® Agilex™ FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Designs Interface Tab
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ FPGA IP
3. Design Example Description for External Memory Interfaces Intel® Agilex™ FPGA IP
4. External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide Archives
5. Document Revision History for External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide

2.1. Creating an EMIF Project

For the Intel® Quartus® Prime software version 17.1 and later, you must create an Intel® Quartus® Prime project before generating the EMIF IP and design example.

  1. Launch the Intel® Quartus® Prime software and select File > New Project Wizard. Click Next.

  2. Specify a directory (<user project directory>), a name for the Intel® Quartus® Prime project (<user project name>), and a top-level design entity name (<user top-level instance name>) that you want to create. Click Next.

  3. Verify that Empty Project is selected. Click Next two times.

  4. Under Family, select Intel® Agilex™ .
  5. Under Name filter, type the device part number.
  6. Under Available devices, select the appropriate device.

  7. Click Finish.
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