Intel® Arria® 10 SX Device Errata and Design Recommendations

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ID 683161
Date 8/03/2022
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Intel® Arria® 10 Design Recommendations 3. Intel® -Specific SoC Errata for Intel® Arria® 10 SX Devices 4. ARM Cortex-A9 MPCore and L2 Cache Errata 5. Document Revision History for Intel® Arria® 10 Device Errata and Design Recommendations
2. Intel® Arria® 10 Design Recommendations x
2.1. Intel® Arria® 10 Device Lifetime Guidance 2.2. SD Card Image Partitioning
2.1. Intel® Arria® 10 Device Lifetime Guidance x
2.1.1. Design Recommendation
3. Intel® -Specific SoC Errata for Intel® Arria® 10 SX Devices x
3.1. Faster Boot Frequency Requires Higher Operating VCCL_HPS Supply 3.2. HPS Shared I/Os Inaccessible If FPGA Configuration Fails 3.3. SD/MMC Power Enable is Inverted 3.4. HPS EMIF Write Performance Degradation When Using ECC and a 16-bit Interface 3.5. Correct Sequence Required When Raising HPS PLL Frequency 3.6. HPS SDRAM ECC Logging Problems 3.7. HPS-to-FPGA Bridges Must Operate at 100 MHz or Above When Using the NoC Timeout Feature 3.8. Rarely, Bus or Bridge Hangs When Configuring or Using HPS SDRAM 3.9. Hard Memory Controller Fails to Exit Self-Refresh Mode 3.10. Automatic Lane Polarity Inversion for PCIe Hard IP 3.11. High VCCBAT Current when VCC is Powered Down 3.12. Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR) 3.13. GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation
4. ARM Cortex-A9 MPCore and L2 Cache Errata x
4.1. Arm* Cortex* -A9 MPU 4.2. Arm* L2 Cache Controller 4.3. Arm* CoreSight PTM
4.1. Arm* Cortex* -A9 MPU x
4.1.1. 761319: Ordering of Read Accesses to the Same Memory Location Might Be Uncertain 4.1.2. 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption 4.1.3. 740657: Global Timer Can Send Two Interrupts for the Same Event 4.1.4. 751476: Missed Watchpoint on the Second Part of an Unaligned Access Crossing a Page Boundary 4.1.5. 754322: Faulty MMU Translations Following ASID Switch 4.1.6. 764369: Data or Unified Cache Line Maintenance by MVA Fails on Inner-Shareable Memory 4.1.7. 794072: A Short Loop Including DMB Instruction Might Cause a Denial of Service When the Other Processor Executes a CP15 Broadcast Operation 4.1.8. 794073: Speculative Instruction Fetches with MMU Disabled Might Not Comply with Architectural Requirements 4.1.9. 794074: A Write Request to an Uncacheable, Shareable Normal Memory Region Might be Executed Twice, Possibly Causing a Software Synchronization Issue 4.1.10. 725631: ISB is Counted in Performance Monitor Events 0x0C and 0x0D 4.1.11. 729817: MainID Register Alias Addresses Are Not Mapped on Debug APB Interface 4.1.12. 729818: In Debug State, the Next Instruction is Stalled When the SDABORT Flag is Set Instead of Being Discarded 4.1.13. 751471: DBGPCSR Format Is Incorrect 4.1.14. 752519: An Imprecise Abort Might Be Reported Twice on Non-Cacheable Reads 4.1.15. 754323: Repeated Store in the Same Cache Line Might Delay the Visibility of the Store 4.1.16. 756421: Sticky Pipeline Advance Bit Cannot be Cleared from Debug APB Accesses 4.1.17. 757119: Some Unallocated Memory Hint Instructions Generate an UNDEFINED Exception Instead of Being Treated as a NOP 4.1.18. 761321: MRC and MCR Are Not Counted in Event 0x68 4.1.19. 764319: Read Accesses to DBGPRSR and DBGPRCR May Generate an Unexpected UNDEF 4.1.20. 771224: Visibility of Debug Enable Access Rights to Enable/Disable Tracking is Not Ensured by an ISB 4.1.21. 775419: PMU Event 0x0A Might Count Twice the LDM PC ^ Instruction with Base Address Register Write-Back
4.2. Arm* L2 Cache Controller x
4.2.1. 754670: A Continuous Write Flow Can Stall a Read Targeting the Same Memory Area 4.2.2. 765569: Prefetcher Can Cross 4 KB Boundary if Offset is Programmed with Value 23 4.2.3. 729815: The High Priority for SO and Dev Reads Feature Can Cause Quality of Service Issues to Cacheable Read Transactions
4.3. Arm* CoreSight PTM x
4.3.1. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow 4.3.2. 711668: Configuration Extension Register Has Wrong Value Status
1. About this Document
2. Intel® Arria® 10 Design Recommendations
3. Intel® -Specific SoC Errata for Intel® Arria® 10 SX Devices
4. ARM Cortex-A9 MPCore and L2 Cache Errata
5. Document Revision History for Intel® Arria® 10 Device Errata and Design Recommendations

3.8. Rarely, Bus or Bridge Hangs When Configuring or Using HPS SDRAM

Description

Under very rare circumstances, an HPS bus or bridge can hang when performing an action involving SDRAM.

The L3 SDRAM interconnect uses an input clock generated by the I/O PLL in FPGA I/O Bank 2K. Immediately after FPGA I/O configuration, while the PLL is settling, the input clock is subject to high frequency transients. The L3 SDRAM interconnect is susceptible to timing violations resulting from these transients. These timing violations can infrequently result in corruption at random locations in the interconnect logic. Symptoms can include:

  • HPS bus hangs when accessing L3 SDRAM interconnect registers
  • HPS bus hangs when accessing HPS SDRAM
  • FPGA master transactions fail to complete when accessing HPS SDRAM through FPGA-to-SDRAM bridge

Workaround

The issue can be avoided if the bootloader follows these guidelines:

  • Always warm reset the HPS after the FPGA I/O is configured
  • Access the SDRAM and the SDRAM interconnect only after the warm reset.

Intel® recommends that you use the SoC EDS v. 17.0, which implements the workaround for both the U-Boot and UEFI bootloaders.

If you need to implement the workaround in a custom bootloader, follow the software guidelines below.

  • Your bootloader will implement a warm reset before allowing any access to the SDRAM or SDRAM controller.

    After the warm reset, the bootloader will execute again. Your code must avoid initiating another warm reset after the first one, or you will create an infinite loop.

    You can use the isw_handoff7 register in the System Manager to keep track of whether the bootloader has previously initiated a warm reset. Prior to the warm reset, store a "magic number" (such as 0xDEADBEEF) in the isw_handoff7 register. This 32-bit register is otherwise unused, and preserved on HPS warm resets.

    Check this register on entry to the bootloader to determine if a warm reset is required. If it is set to the "magic number", clear it, and skip the warm reset, to avoid an infinite loop.

    Note: Your bootloader code should be re-entrant.
  • After the FPGA I/O is configured, and before initiating the warm reset, insert a delay of ( 1 ms + 65,536 × trefclk ), where trefclk is the reference clock period. This delay allows the I/O PLL to lock and the associated circuitry to settle.
  • Use the warm RAM boot feature, so that on the warm reset, the bootloader is re-entered without the BootROM trying to load again from flash. To use this feature, configure the System Manager warmram_* registers, as described in "Boot ROM Flow" and "Boot ROM Code" in the Intel® Intel® Arria® 10 Hard Processor System Technical Reference Manual.
  • Access the SDRAM and the SDRAM interconnect only after the warm reset.
Note:

During the HPS warm reset workaround loop, your system must not:

  • Reconfigure the FPGA I/O
  • Reset the HPS EMIF module

Status

Affects: All Intel® Arria® 10 SX devices

Status: No device fix planned. Fixed in the SoC EDS v. 17.0. An SoC EDS patch is available for earlier versions.

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