Visible to Intel only — GUID: cru1462840331846
Ixiasoft
Visible to Intel only — GUID: cru1462840331846
Ixiasoft
3.5. Correct Sequence Required When Raising HPS PLL Frequency
Description
The Arria 10 SoC device family requires a specific programming sequence to raise the HPS PLL frequency. Your software must follow this sequence to ensure stable PLL operation and prevent system issues such as boot failure.
Workaround
Increase the PLL frequency in discrete step changes of no more than 100 MHz, with a 1 ms waiting period between step changes. Between each step change, verify PLL lock. You can verify PLL lock as follows:
- Read the intrs register in the clock manager.
- Set an interrupt in the intren register of the clock manager
For example, you can increase the PLL frequency from 900 MHz to 1200 MHz with the following steps:
- Increase the frequency from 900 MHz to 1000 MHz
- Wait 1 ms
- Verify PLL lock
- Increase the frequency from 1000 MHz to 1100 MHz
- Wait 1 ms
- Verify PLL lock
- Increase the frequency from 1100 MHz to 1200 MHz
If you set up the PLL programming manually, follow the sequence above.
Status
Affects: All Arria 10 SX devices
Status: ACS patch 0.02soc, applicable to SoC EDS 16.0, corrects this issue by updating U-boot to manage PLL frequency transitions properly. A future SoC EDS release will resolve this issue for both U-boot and UEFI applications.