Intel® Arria® 10 SX Device Errata and Design Recommendations

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ID 683161
Date 8/03/2022
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Intel® Arria® 10 Design Recommendations 3. Intel® -Specific SoC Errata for Intel® Arria® 10 SX Devices 4. ARM Cortex-A9 MPCore and L2 Cache Errata 5. Document Revision History for Intel® Arria® 10 Device Errata and Design Recommendations
2. Intel® Arria® 10 Design Recommendations x
2.1. Intel® Arria® 10 Device Lifetime Guidance 2.2. SD Card Image Partitioning
2.1. Intel® Arria® 10 Device Lifetime Guidance x
2.1.1. Design Recommendation
3. Intel® -Specific SoC Errata for Intel® Arria® 10 SX Devices x
3.1. Faster Boot Frequency Requires Higher Operating VCCL_HPS Supply 3.2. HPS Shared I/Os Inaccessible If FPGA Configuration Fails 3.3. SD/MMC Power Enable is Inverted 3.4. HPS EMIF Write Performance Degradation When Using ECC and a 16-bit Interface 3.5. Correct Sequence Required When Raising HPS PLL Frequency 3.6. HPS SDRAM ECC Logging Problems 3.7. HPS-to-FPGA Bridges Must Operate at 100 MHz or Above When Using the NoC Timeout Feature 3.8. Rarely, Bus or Bridge Hangs When Configuring or Using HPS SDRAM 3.9. Hard Memory Controller Fails to Exit Self-Refresh Mode 3.10. Automatic Lane Polarity Inversion for PCIe Hard IP 3.11. High VCCBAT Current when VCC is Powered Down 3.12. Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR) 3.13. GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation
4. ARM Cortex-A9 MPCore and L2 Cache Errata x
4.1. Arm* Cortex* -A9 MPU 4.2. Arm* L2 Cache Controller 4.3. Arm* CoreSight PTM
4.1. Arm* Cortex* -A9 MPU x
4.1.1. 761319: Ordering of Read Accesses to the Same Memory Location Might Be Uncertain 4.1.2. 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption 4.1.3. 740657: Global Timer Can Send Two Interrupts for the Same Event 4.1.4. 751476: Missed Watchpoint on the Second Part of an Unaligned Access Crossing a Page Boundary 4.1.5. 754322: Faulty MMU Translations Following ASID Switch 4.1.6. 764369: Data or Unified Cache Line Maintenance by MVA Fails on Inner-Shareable Memory 4.1.7. 794072: A Short Loop Including DMB Instruction Might Cause a Denial of Service When the Other Processor Executes a CP15 Broadcast Operation 4.1.8. 794073: Speculative Instruction Fetches with MMU Disabled Might Not Comply with Architectural Requirements 4.1.9. 794074: A Write Request to an Uncacheable, Shareable Normal Memory Region Might be Executed Twice, Possibly Causing a Software Synchronization Issue Description Impact Workaround Category 4.1.10. 725631: ISB is Counted in Performance Monitor Events 0x0C and 0x0D 4.1.11. 729817: MainID Register Alias Addresses Are Not Mapped on Debug APB Interface 4.1.12. 729818: In Debug State, the Next Instruction is Stalled When the SDABORT Flag is Set Instead of Being Discarded 4.1.13. 751471: DBGPCSR Format Is Incorrect 4.1.14. 752519: An Imprecise Abort Might Be Reported Twice on Non-Cacheable Reads 4.1.15. 754323: Repeated Store in the Same Cache Line Might Delay the Visibility of the Store 4.1.16. 756421: Sticky Pipeline Advance Bit Cannot be Cleared from Debug APB Accesses 4.1.17. 757119: Some Unallocated Memory Hint Instructions Generate an UNDEFINED Exception Instead of Being Treated as a NOP 4.1.18. 761321: MRC and MCR Are Not Counted in Event 0x68 4.1.19. 764319: Read Accesses to DBGPRSR and DBGPRCR May Generate an Unexpected UNDEF 4.1.20. 771224: Visibility of Debug Enable Access Rights to Enable/Disable Tracking is Not Ensured by an ISB 4.1.21. 775419: PMU Event 0x0A Might Count Twice the LDM PC ^ Instruction with Base Address Register Write-Back
4.2. Arm* L2 Cache Controller x
4.2.1. 754670: A Continuous Write Flow Can Stall a Read Targeting the Same Memory Area 4.2.2. 765569: Prefetcher Can Cross 4 KB Boundary if Offset is Programmed with Value 23 4.2.3. 729815: The High Priority for SO and Dev Reads Feature Can Cause Quality of Service Issues to Cacheable Read Transactions
4.3. Arm* CoreSight PTM x
4.3.1. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow 4.3.2. 711668: Configuration Extension Register Has Wrong Value Status
1. About this Document
2. Intel® Arria® 10 Design Recommendations
3. Intel® -Specific SoC Errata for Intel® Arria® 10 SX Devices
4. ARM Cortex-A9 MPCore and L2 Cache Errata
5. Document Revision History for Intel® Arria® 10 Device Errata and Design Recommendations

4.1.9. 794074: A Write Request to an Uncacheable, Shareable Normal Memory Region Might be Executed Twice, Possibly Causing a Software Synchronization Issue

Description

Under certain timing circumstances specific to the Cortex* -A9 microarchitecture, a write request to an uncacheable, shareable normal memory region might be executed twice, causing the write request to be sent twice on the AXI bus. This condition might happen when the write request is followed by another write into the same naturally doubleword-aligned memory region, without a DMB between the two writes.

The repetition of the write usually has no impact on the overall behavior of the system, unless the repeated write is used for synchronization purposes.

This erratum requires the following conditions:

  • A write request is performed to an uncacheable, shareable normal memory region.
  • Another write request is performed into the same naturally doubleword-aligned memory region. This second write request must not be performed to the exact same bytes as the first store.

A write request to normal memory region is treated as uncacheable in the following cases:

  • The write request occurs while the data cache is disabled.
  • The write request is targeting a memory region marked as normal memory non-cacheable or cacheable write-through.
  • The write request is targeting a memory region marked as normal memory cacheable write-back and shareable, and the CPU is in AMP mode.

Impact

This erratum might have implications in a multi-master system where control information is passed between several processing elements in memory using a communication variable, such as a semaphore. In this type of system, it is common for communication variables to be claimed using a Load-Exclusive/Store-Exclusive, but for the communication variable to be cleared using a non-Exclusive store. This erratum means that the clearing of such a communication variable might occur twice. This error might lead to two masters apparently claiming a communication variable, and therefore might cause data corruption to shared data.

A scenario in which this might happen is: 

MOV r1,#0x40                  ;address is double-word aligned, mapped in 
				              ;Normal Non-cacheable Shareable memory
Loop: LDREX r5, [r1,#0x0]     ;read the communication variable
CMP r5, #0                    ;check if 0  
STREXEQ r5, r0, [r1]          ;attempt to store new value
CMPEQ r5, #0                  ;test if store succeeded
BNE Loop                      ;retry if not
DMB                           ;ensures that all subsequent accesses are observed when 
                              ;gaining of the communication variable has been observed  
                              ;loads and stores in the critical region can now be performed 
MOV r2,#0
MOV r0, #0
DMB                           ;ensure all previous accesses are observed before the 
                              ;communication variable is cleared
STR r0, [r1]                  ;clear the communication variable with normal store
STR r2, [r1,#0x4]             ;previous STR might merge and be sent again, which 
                              ;might cause undesired release of the communication 
                              ;variable.

This scenario is valid when the communication variable is a byte, a half-word, or a word.

Workaround

There are several possible workarounds:

  • Add a DMB after clearing a communication variable:
    STR r0, [r1]     ;clear the communication variable
DMB              ;ensure the previous STR is complete
    Also, any IRQ or FIQ handler must execute a DMB at the start to ensure that the clear of any communication variable is complete.
  • Ensure there is no other data using the same naturally aligned 64-bit memory location as the communication variable:
    ALIGN 64
communication_variable DCD 0 
unsed_data DCD 0
LDR r1 = communication_variable
  • Use a Store-Exclusive to clear the communication variable, rather than a non-Exclusive store.

Category

Category 3

Level Two Title