Intel® Arria® 10 SX Device Errata and Design Recommendations

Download PDF
ID 683161
Date 8/03/2022
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Intel® Arria® 10 Design Recommendations 3. Intel® -Specific SoC Errata for Intel® Arria® 10 SX Devices 4. ARM Cortex-A9 MPCore and L2 Cache Errata 5. Document Revision History for Intel® Arria® 10 Device Errata and Design Recommendations
2. Intel® Arria® 10 Design Recommendations x
2.1. Intel® Arria® 10 Device Lifetime Guidance 2.2. SD Card Image Partitioning
2.1. Intel® Arria® 10 Device Lifetime Guidance x
2.1.1. Design Recommendation
3. Intel® -Specific SoC Errata for Intel® Arria® 10 SX Devices x
3.1. Faster Boot Frequency Requires Higher Operating VCCL_HPS Supply 3.2. HPS Shared I/Os Inaccessible If FPGA Configuration Fails 3.3. SD/MMC Power Enable is Inverted 3.4. HPS EMIF Write Performance Degradation When Using ECC and a 16-bit Interface 3.5. Correct Sequence Required When Raising HPS PLL Frequency 3.6. HPS SDRAM ECC Logging Problems 3.7. HPS-to-FPGA Bridges Must Operate at 100 MHz or Above When Using the NoC Timeout Feature 3.8. Rarely, Bus or Bridge Hangs When Configuring or Using HPS SDRAM 3.9. Hard Memory Controller Fails to Exit Self-Refresh Mode 3.10. Automatic Lane Polarity Inversion for PCIe Hard IP 3.11. High VCCBAT Current when VCC is Powered Down 3.12. Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR) 3.13. GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation
4. ARM Cortex-A9 MPCore and L2 Cache Errata x
4.1. Arm* Cortex* -A9 MPU 4.2. Arm* L2 Cache Controller 4.3. Arm* CoreSight PTM
4.1. Arm* Cortex* -A9 MPU x
4.1.1. 761319: Ordering of Read Accesses to the Same Memory Location Might Be Uncertain 4.1.2. 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption 4.1.3. 740657: Global Timer Can Send Two Interrupts for the Same Event 4.1.4. 751476: Missed Watchpoint on the Second Part of an Unaligned Access Crossing a Page Boundary 4.1.5. 754322: Faulty MMU Translations Following ASID Switch 4.1.6. 764369: Data or Unified Cache Line Maintenance by MVA Fails on Inner-Shareable Memory Description Impact Workaround Category 4.1.7. 794072: A Short Loop Including DMB Instruction Might Cause a Denial of Service When the Other Processor Executes a CP15 Broadcast Operation 4.1.8. 794073: Speculative Instruction Fetches with MMU Disabled Might Not Comply with Architectural Requirements 4.1.9. 794074: A Write Request to an Uncacheable, Shareable Normal Memory Region Might be Executed Twice, Possibly Causing a Software Synchronization Issue 4.1.10. 725631: ISB is Counted in Performance Monitor Events 0x0C and 0x0D 4.1.11. 729817: MainID Register Alias Addresses Are Not Mapped on Debug APB Interface 4.1.12. 729818: In Debug State, the Next Instruction is Stalled When the SDABORT Flag is Set Instead of Being Discarded 4.1.13. 751471: DBGPCSR Format Is Incorrect 4.1.14. 752519: An Imprecise Abort Might Be Reported Twice on Non-Cacheable Reads 4.1.15. 754323: Repeated Store in the Same Cache Line Might Delay the Visibility of the Store 4.1.16. 756421: Sticky Pipeline Advance Bit Cannot be Cleared from Debug APB Accesses 4.1.17. 757119: Some Unallocated Memory Hint Instructions Generate an UNDEFINED Exception Instead of Being Treated as a NOP 4.1.18. 761321: MRC and MCR Are Not Counted in Event 0x68 4.1.19. 764319: Read Accesses to DBGPRSR and DBGPRCR May Generate an Unexpected UNDEF 4.1.20. 771224: Visibility of Debug Enable Access Rights to Enable/Disable Tracking is Not Ensured by an ISB 4.1.21. 775419: PMU Event 0x0A Might Count Twice the LDM PC ^ Instruction with Base Address Register Write-Back
4.2. Arm* L2 Cache Controller x
4.2.1. 754670: A Continuous Write Flow Can Stall a Read Targeting the Same Memory Area 4.2.2. 765569: Prefetcher Can Cross 4 KB Boundary if Offset is Programmed with Value 23 4.2.3. 729815: The High Priority for SO and Dev Reads Feature Can Cause Quality of Service Issues to Cacheable Read Transactions
4.3. Arm* CoreSight PTM x
4.3.1. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow 4.3.2. 711668: Configuration Extension Register Has Wrong Value Status
1. About this Document
2. Intel® Arria® 10 Design Recommendations
3. Intel® -Specific SoC Errata for Intel® Arria® 10 SX Devices
4. ARM Cortex-A9 MPCore and L2 Cache Errata
5. Document Revision History for Intel® Arria® 10 Device Errata and Design Recommendations

4.1.6. 764369: Data or Unified Cache Line Maintenance by MVA Fails on Inner-Shareable Memory

Description

Under certain timing circumstances, a data or unified cache line maintenance operation by Modified Virtual Addresses (MVA) that targets an inner-shareable memory region might fail to propagate to either the Point of Coherency (PoC) or to the Point of Unification (PoU) of the system.

As a consequence, the visibility of the updated data might not be guaranteed to either the instruction side, in the case of self-modifying code, or to an external non-coherent agent, such as a DMA engine.

This erratum requires a dual Cortex* -A9 MPCore* device working in Symmetric Multi-Processing (SMP) mode with the broadcasting of CP15 maintenance operations enabled.

The following scenario shows how this erratum can occur:

  1. One CPU performs a data or unified cache line maintenance operation by MVA targeting a memory region that is locally dirty.
  2. The second CPU issues a memory request targeting this same memory location within the same time frame.

A race condition can occur, resulting in the cache operation not being performed to the specified Point of Unification or Point of Coherence.

This erratum affects the following maintenance operations:
  • DCIMVAC: Invalidate data or unified cache line by MVA to PoC.
  • DCCMVAC: Clean data or unified cache line by MVA to PoC.
  • DCCMVAU: Clean data or unified cache line by MVA to PoU.
  • DCCIMVAC: Clean and invalidate data or unified cache line by MVA to PoC.

This erratum can occur when the second CPU performs any of the following operations:

  • A read request resulting from a Load instruction; the Load might be a speculative one.
  • A write request resulting from any Store instruction.
  • A data prefetch resulting from a PLD instruction; the PLD might be a speculative one.

Impact

Because it is uncertain whether execution of the cache maintenance operation propagates to either the Point of Unification or the Point of Coherence, stale data might remain in the data cache and not become visible to other agents that should have gained visibility to it.

Note that the data remains coherent on the L1 data side. Any data read from the other processor in the Cortex* -A9 MPCore* cluster, or from the Accelerator Coherency Port (ACP), would see the correct data. In the same way, any write to the same cache line from the other processor in the Cortex* -A9 MPCore* cluster, or from the ACP, does not cause a data corruption resulting from a loss of either data.

Consequently, the failure can only impact non-coherent agents in the system. These agents can be either the instruction cache of the processor, in the case of self-modifying code, or any non-coherent external agent in the system such as a DMA.

Workaround

Two workarounds are available for this erratum.

The first workaround requires the three following elements to be applied together:

  • Set bit[0] in the undocumented SCU Diagnostic Control register located at offset 0x30 from the PERIPHBASE address. Setting this bit disables the “migratory line” feature and forces a dirty cache line to be evicted to the lower memory subsystem, which is both the Point of Coherency and the Point of Unification, when it is being read by another processor. Note that this bit can be written, but is always read as zero.
  • Insert a DSB instruction before the cache maintenance operation. Note that if the cache maintenance operation executes within a loop that performs no other memory operations, ARM recommends only adding a DSB before entering the loop.
  • Ensure there is no false sharing (on a cache line size alignment) for self-modifying code or for data produced for external non-coherent agent such as a DMA engine. For systems that cannot prevent false sharing in these regions, this third step can be replaced by performing the sequence of DSB followed by a cache maintenance operation twice.

Note that even when all three components of the workaround are in place, this erratum might still occur. However, this occurrence would require some extremely rare and complex timing conditions, so that the probability of reaching the point of failure is extremely low. This low probability, along with the fact that this erratum requires an uncommon software scenario, explains why this workaround is likely to be a reliable practical solution for most systems.

To ARM's knowledge, no failure has been observed in any system when all three components of this workaround have been implemented.

For critical systems that cannot cope with the extremely low failure risks associated with the above workaround, a second workaround is possible which involves changing the mapping of the data being accessed so that it is in a non-cacheable area. This ensures that the written data remains uncached, which means it is always visible to non-coherent agents in the system, or to the instruction side in the case of self-modifying code, without any need for cache maintenance operation.

Category

Category 3

Level Two Title