Visible to Intel only — GUID: eis1415255951821
Ixiasoft
1.1. ALTDDIO Features
1.2. ALTDDIO Common Applications
1.3. ALTDDIO Resource Utilization and Performance
1.4. ALTDDIO Parameter Settings
1.5. ALTDDIO Functional Description
1.6. Design Example: 8-Bit DDR Divider Using ALTDDIO_BIDIR
1.7. ALTDDIO_IN IP Core Signals
1.8. ALTDDIO_OUT IP Core Signals
1.9. ALTDDIO_BIDIR IP Core Signals
1.10. Verilog HDL Prototype
1.11. VHDL Component Declaration
1.12. VHDL LIBRARY-USE Declaration
1.13. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide Archives
1.14. Document Revision History
Visible to Intel only — GUID: eis1415255951821
Ixiasoft
1.6.3. Implement the Divider Design
This section describes how to assign the Stratix® EP1S10F780C6 device to the project and compile the project.
- With the ex2.qar project open, on the Assignments menu, click Settings. The Settings dialog box displays.
- In the Category list, select Device.
- To answer Which device family will you be using?, select Stratix® .
- Under Target device, select Specific device selected in ‘Available devices’ list.
- In the Available devices list, select EP1S10F780C6.
- Under Show in ‘Available devices’ list, select FBGA as the Package, Pin count of 780, Speed grade of 6, and turn on Show Advanced Devices.
- Click OK.
- On the Processing menu, click Start Compilation.
- When the Full Compilation was successful box displays, click OK.