Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide

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ID 683148
Date 6/19/2017
Public
Document Table of Contents
Document Table of Contents x
1. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide
1. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide x
1.1. ALTDDIO Features 1.2. ALTDDIO Common Applications 1.3. ALTDDIO Resource Utilization and Performance 1.4. ALTDDIO Parameter Settings 1.5. ALTDDIO Functional Description 1.6. Design Example: 8-Bit DDR Divider Using ALTDDIO_BIDIR 1.7. ALTDDIO_IN IP Core Signals 1.8. ALTDDIO_OUT IP Core Signals 1.9. ALTDDIO_BIDIR IP Core Signals 1.10. Verilog HDL Prototype 1.11. VHDL Component Declaration 1.12. VHDL LIBRARY-USE Declaration 1.13. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide Archives 1.14. Document Revision History
1.2. ALTDDIO Common Applications x
1.2.1. DDR SDRAM, DDR2 SDRAM and RLDRAM II Memory 1.2.2. QDR SRAM and QDRII SRAM Memory Interfaces 1.2.3. High-Speed Interface Applications
1.5. ALTDDIO Functional Description x
1.5.1. DDR Device Configuration 1.5.2. DDR I/O Timing
1.5.1. DDR Device Configuration x
1.5.1.1. Input Configuration 1.5.1.2. Output Configuration 1.5.1.3. Bidirectional Configuration
1.6. Design Example: 8-Bit DDR Divider Using ALTDDIO_BIDIR x
1.6.1. Generate a Divider Using ALTDDIO_BIDIR 1.6.2. Create a Divider 1.6.3. Implement the Divider Design 1.6.4. Functional Results—Simulate the Divider Design in the ModelSim* - Intel® FPGA Edition Software
1.6.1. Generate a Divider Using ALTDDIO_BIDIR x
1.6.1.1. Create the ALTDDIO_BIDIR IP Core 1.6.1.2. Create the LPM_DIVIDE IP core
1. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide

1.6.1.2. Create the LPM_DIVIDE IP core

Follow these steps to create the lpm_divide IP core.
  1. On the Tools menu, select IP Catalog.
  2. In the IP catalog, double-click LPM_DIVIDE.
  3. Specify the IP variation file name and click OK.
  4. In the parameter editor pages, select or verify the configuration settings shown in the following table. Click Next to advance from one page to the next.
    Page Parameter Value
    2a Which megafunction would you like to customize In the Arithmetic folder, select LPM_DIVIDE
    Which device family will you be using? Stratix
    Which type of output file do you want to create? VHDL
    What name do you want for the output file? lp_div
    Return to this page for another create operation Turned off
    3 Currently selected device family Stratix IV
    Match project/default Turned on
    How wide should the ‘numerator’ input bus be? 8
    How wide should the ‘denominator’ input bus be? 8
    Numerator Representation Select Unsigned
    Denominator Representation Select Unsigned
    4 Do you want to pipeline the function? Select Yes, I want an output latency of 1 clock cycle
    Create an Asynchronous Clear input Turned off
    Create a Clock Enable input Turned off
    Which do you wish to optimize? Select Default Optimization
    Always return a positive remainder? Select Yes
    5 Generate netlist Turned off
    6 Variation file Turned on
    Quartus II IP file Turned on
    Quartus II symbol file (.bsf) Turned off
    Instantiation template file Turned on
    Verilog HDL black box file (_bb.v) Turned on
    AHDL Include file (.inc) Turned off
    VHDL component declaration file (.cmp) Turned on
    PinPlanner ports file (.PPF) Turned on
  5. Click Finish.

    The lpm_divide IP core variation is now built.

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