Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide

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ID 683148
Date 6/19/2017
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Document Table of Contents
Document Table of Contents x
1. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide
1. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide x
1.1. ALTDDIO Features 1.2. ALTDDIO Common Applications 1.3. ALTDDIO Resource Utilization and Performance 1.4. ALTDDIO Parameter Settings 1.5. ALTDDIO Functional Description 1.6. Design Example: 8-Bit DDR Divider Using ALTDDIO_BIDIR 1.7. ALTDDIO_IN IP Core Signals 1.8. ALTDDIO_OUT IP Core Signals 1.9. ALTDDIO_BIDIR IP Core Signals 1.10. Verilog HDL Prototype 1.11. VHDL Component Declaration 1.12. VHDL LIBRARY-USE Declaration 1.13. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide Archives 1.14. Document Revision History
1.2. ALTDDIO Common Applications x
1.2.1. DDR SDRAM, DDR2 SDRAM and RLDRAM II Memory 1.2.2. QDR SRAM and QDRII SRAM Memory Interfaces 1.2.3. High-Speed Interface Applications
1.5. ALTDDIO Functional Description x
1.5.1. DDR Device Configuration 1.5.2. DDR I/O Timing
1.5.1. DDR Device Configuration x
1.5.1.1. Input Configuration 1.5.1.2. Output Configuration 1.5.1.3. Bidirectional Configuration
1.6. Design Example: 8-Bit DDR Divider Using ALTDDIO_BIDIR x
1.6.1. Generate a Divider Using ALTDDIO_BIDIR 1.6.2. Create a Divider 1.6.3. Implement the Divider Design 1.6.4. Functional Results—Simulate the Divider Design in the ModelSim* - Intel® FPGA Edition Software
1.6.1. Generate a Divider Using ALTDDIO_BIDIR x
1.6.1.1. Create the ALTDDIO_BIDIR IP Core 1.6.1.2. Create the LPM_DIVIDE IP core
1. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide

1. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide

Updated for:
Intel® Quartus® Prime Design Suite 17.0

The ALTDDIO IP cores configure the DDR I/O registers in APEX™ II, Arria® II, Arria® V, Cyclone® IV, Cyclone® V, Cyclone® 10 LP, HardCopy®, Stratix® IV, and Stratix® V devices.

You can also use these IP cores to implement DDR registers in the logic elements (LEs). In Arria®  GX, Stratix® series, HardCopy II, HardCopy  Stratix® , and APEX™ II devices, the DDR registers are implemented in the I/O element (IOE). In Cyclone® series devices, the IP cores automatically implement the DDR registers in the LEs closest to the pin. The ALTDDIO_IN IP core implements the interface for DDR inputs. The ALTDDIO_OUT IP core implements the interface for DDR outputs. The ALTDDIO_BIDIR IP core implements the interface for bidirectional DDR inputs and outputs.

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