SDI II Intel® FPGA IP User Guide

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ID 683133
Date 10/05/2023
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Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Quick Reference 2. SDI II IP Core Overview 3. SDI II IP Core Getting Started 4. SDI II IP Core Parameters 5. SDI II IP Core Functional Description 6. SDI II IP Core Signals 7. SDI II IP Core Design Considerations 8. SDI II IP Core Testbench and Design Examples 9. SDI II Intel® FPGA IP User Guide Archives 10. Document Revision History for the SDI II Intel® FPGA IP User Guide
2. SDI II IP Core Overview x
2.1. Release Information 2.2. Device Family Support 2.3. General Description 2.4. Performance and Resource Utilization
3. SDI II IP Core Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Design Walkthrough 3.3. SDI II IP Core Component Files 3.4. Compiling the SDI II IP Core Design 3.5. Programming an FPGA
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.2. Design Walkthrough x
3.2.1. Creating a New Intel® Quartus® Prime Project 3.2.2. Launching IP Catalog 3.2.3. Parameterizing the IP Core 3.2.4. Generating a Design Example and Simulation Testbench
5. SDI II IP Core Functional Description x
5.1. Protocol 5.2. Transceiver 5.3. Submodules 5.4. Optional Features
5.1. Protocol x
5.1.1. Transmitter 5.1.2. Receiver
5.3. Submodules x
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
5.4. Optional Features x
5.4.1. HD-SDI Dual Link to 3G-SDI (Level B) Conversion 5.4.2. 3G-SDI (Level B) to HD-SDI Dual Link Conversion 5.4.3. SMPTE RP168 Switching Support 5.4.4. SD 20-Bit Interface for Dual/Triple Rate 5.4.5. Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices 5.4.6. Intel FPGA Video Streaming Interface
5.4.6. Intel FPGA Video Streaming Interface x
5.4.6.1. RGB Pixel Packing 5.4.6.2. YCbCr 444 Pixel Packing 5.4.6.3. YCbCr 422 Pixel Packing 5.4.6.4. Supported Modes
6. SDI II IP Core Signals x
6.1. SDI II IP Core Resets and Clocks 6.2. Transmitter Protocol Signals 6.3. Receiver Protocol Signals 6.4. Transceiver Signals 6.5. Transmitter Streaming Video and Control Signals 6.6. Receiver Streaming Video and Control Signals
6.2. Transmitter Protocol Signals x
6.2.1. Image Mapping
6.3. Receiver Protocol Signals x
6.3.1. rx_format
7. SDI II IP Core Design Considerations x
7.1. Transceiver Handling Guidelines 7.2. Timing Violation 7.3. SDI II IP Core Registers
7.1. Transceiver Handling Guidelines x
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices 7.1.2. Handling Transceiver in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices 7.1.3. Handling Transceiver in Intel Agilex® 7 F-Tile Devices
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices x
7.1.1.1. Modifying the Transceiver Reconfiguration Controller 7.1.1.2. Modifying the Reconfiguration Management 7.1.1.3. Modifying the Reconfiguration Router
7.1.2. Handling Transceiver in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices x
7.1.2.1. Changing RX CDR Reference Clock in Transceiver Native PHY IP Core 7.1.2.2. Merging Simplex Mode Transceiver in the Same Channel 7.1.2.3. Using Generated Reconfiguration Management for Triple and Multi Rates 7.1.2.4. Ensuring Independent RX and TX Operations in the Same Channel 7.1.2.5. Potential Routing Problem During Fitter Stage in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 7.1.2.6. Unconstrained Clocks in SDI Multi-Rate RX Using Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 7.1.2.7. Unused Transceiver Channels 7.1.2.8. Routing Transceiver Reference Clock Pins to Core Logic in Intel® Stratix® 10 Devices
7.1.3. Handling Transceiver in Intel Agilex® 7 F-Tile Devices x
7.1.3.1. System PLL Clocking Mode 7.1.3.2. RX Transceiver Settings 7.1.3.3. TX Transceiver Settings 7.1.3.4. Unused Transceiver Tiles 7.1.3.5. Dynamic Reconfiguration 7.1.3.6. SD-SDI Timing Jitter With External VCXO Which Receive FVH Sync Signals
7.1.3.2. RX Transceiver Settings x
7.1.3.2.1. Multi-rate Designs 7.1.3.2.2. Triple-rate Designs 7.1.3.2.3. Single-rate Designs
7.3. SDI II IP Core Registers x
7.3.1. SDI II Tx Register Summary 7.3.2. SDI II Tx Register Description 7.3.3. SDI II Rx Register Summary 7.3.4. SDI II Rx Register Description
8. SDI II IP Core Testbench and Design Examples x
8.1. Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile Devices 8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices
8.1. Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile Devices x
8.1.1. Design Example Presets
8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices x
8.2.1. Design Example Components 8.2.2. Design Reference 8.2.3. Simulating the SDI II IP Core Design
8.2.1. Design Example Components x
8.2.1.1. Video Pattern Generator 8.2.1.2. Transceiver Reconfiguration Controller 8.2.1.3. Reconfiguration Management 8.2.1.4. Reconfiguration Router 8.2.1.5. Avalon® Memory-Mapped Interface Translators
8.2.2. Design Reference x
8.2.2.1. Video Pattern Generator Signals 8.2.2.2. Transceiver Reconfiguration Controller Signals 8.2.2.3. Reconfiguration Management Parameters 8.2.2.4. Reconfiguration Router Signals
8.2.3. Simulating the SDI II IP Core Design x
8.2.3.1. Simulation Run Time
1. SDI II Intel® FPGA IP Quick Reference
2. SDI II IP Core Overview
3. SDI II IP Core Getting Started
4. SDI II IP Core Parameters
5. SDI II IP Core Functional Description
6. SDI II IP Core Signals
7. SDI II IP Core Design Considerations
8. SDI II IP Core Testbench and Design Examples
9. SDI II Intel® FPGA IP User Guide Archives
10. Document Revision History for the SDI II Intel® FPGA IP User Guide

6.2. Transmitter Protocol Signals

Table 19.  Transmitter Protocol Signals—Synchronous to tx_pclk
Note: S = Indicates the number of 20-bit interfaces; 4 for multi-rate (up to 12G) mode and 1 for other modes.
Signal Width Direction Description
tx_enable_crc 4 1 Input Enables CRC insertion for all modes except SD-SDI.
tx_enable_ln 4 1 Input Enables LN insertion for all modes except SD-SDI.
tx_std 5 3 Input

Transmitter video standard with multiplexed 10-bit parallel interface:

  • SD-SDI = 000
  • HD-SDI = 001
  • 3G-SDI Level A 10-bit Multiplex= 011
  • 3G-SDI Level B 10-bit Multiplex= 010
  • 6G-SDI 10-bit Multiplex Type 1 = 101
  • 6G-SDI 10-bit Multiplex Type 2 = 100
  • 12G-SDI 10-bit Multiplex Type 1 = 111
  • 12G-SDI 10-bit Multiplex Type 2= 110
Note: Applicable for 3G-SDI, and dual-rate, triple-rate, and multi-rate modes.

For 6G and 12G-SDI, there are a few modes of data mapping for different image formats, and each of these modes requires a different type of 10-bit Multiplex interface. It is important to find out which mode you are transmitting and assign the proper value of the 10-bit Multiplex interface of that mode.

For instance, Single link 6G-SDI has three modes of Data Mapping (Mode 1 – Mode 3). Mode 2 and Mode 3 are assigned to 10-bit Multiplex Type 1 according to SMPTE ST2081-10.

As for Single Link 6G-SDI Mode 1, it is assigned to 10-bit Multiplex Type 2.

This signal is only applicable for 3G, dual rate, triple rate and multi rate.
tx_datain 5 20S Input

User-supplied transmitter parallel data.

  • SD-SDI = bits 19:10 unused; bits 9:0 C, Y multiplex
  • HD-SDI = bits 19:10 Y; bits 9:0 C
  • HD-SDI dual link = bits 19:10 Y link A, bits 9:0 C link A
  • 3G-SDI Level A = bits 19:10 Y; bits 9:0 C
  • 3G-SDI Level B = bits 19:10 C, Y multiplex (link A); bits 9:0 C, Y multiplex (link B)
  • 6G-SDI: bits 79:40 unused; bits 39:30 data stream 1; bits 29:20 data stream 2; bit 19:10 data stream 3; bits 9:0 data stream 4.
  • 12G-SDI: bits 79:70 data stream 1; bits 69:60 data stream 2; bit 59:50 data stream 3; bits 49:40 data stream 4; bits 39:30 data stream 5; bits 29:20 stream 6; bits 19:10 stream 7; bits 9:0 data stream 8

Refer to Image Mapping for more information about the 6G-SDI and 12G-SDI image mapping.

For transceiver only configurations, the transmitter does not scramble these data before sending to the Native PHY IP core.

tx_datain_b 20 Input

User-supplied transmitter parallel data for link B.

HD-SDI dual link = bits 19:10 Y link B, bits 9:0 C link B

For transceiver only configurations, the transmitter does not scramble these data before sending to the Native PHY IP core.

Note: For HD-SDI dual link mode only.
tx_datain_valid 5 1 Input

Transmitter parallel data valid. The timing (H: High, L: Low) must be synchronous to tx_pclk clock domain and has the following settings:

  • SD-SDI = 1H 4L 1H 5L
  • HD-SDI = H
  • 3G-SDI = H
  • HD-SDI Dual Link = H
  • Dual rate = SD (1H 4L 1H 5L); HD (1H 1L)
  • Triple rate = SD (1H 4L 1H 5L); HD (1H 1L); 3G (H)
  • Multi rate (up to 12G) = SD (1H 4L 1H 5L); HD (1H 1L); 3G/6G/12G (H)

This signal can be driven by user logic or by the tx_dataout_valid signal for SD-SDI, and dual-rate, triple-rate, and multi-rate modes.

tx_datain_valid_b 1 Input

Transmitter parallel data valid for link B. Applicable for HD-SDI dual link mode only.

HD-SDI dual link = H

This signal can be driven by user logic or by the tx_dataout_valid_b signal.

tx_trs 1 Input

Transmitter TRS input.

Assert this signal on the first word of both EAV and SAV TRSs.
  • For 3G level B, 6G or 12G 10-bit Multiplex Type 2, first word means two tx_pclk cycles.
  • For the other modes, first word means one tx_pclk cycle.
Note:
  1. Not applicable for transceiver configurations.
  2. Not applicable when Enable active video data protocols = AXIS-VVP Full.
tx_trs_b 1 Input

Transmitter TRS input for link B.

Note: For HD-SDI dual link combined or protocol only configurations.
tx_ln 5 11S Input

Transmitter line number. For Payload ID insertion, drive this signal with valid values.

Not applicable when you disable the Insert Video Payload ID (SMPTE ST 352) option in SD-SDI.

tx_ln_b 11S Input

Transmitter line number for link B. For Payload ID insertion, drive this signal with valid values.

For use in 3G-SDI, HD-SDI dual link, triple-rate, and multi-rate (up to 12G-SDI) line number insertion.

tx_dataout 20S Output
Transmitter parallel data out.
  • Arria V, Cyclone V, and Stratix V devices: Available for transmitter protocol configuration only.
  • Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile devices: Available whenever TX core is included.
tx_dataout_b 20 Output

Transmitter parallel data out for link B.

Note: Applicable for HD-SDI dual link transmitter protocol configuration only.
tx_dataout_valid 1 Output

Data valid generated by the core. This signal can be used to drive tx_datain_valid. The timing (H: High, L: Low) must be synchronous to tx_pclk clock domain and have the following settings:

  • SD-SDI = 1H 4L 1H 5L
  • HD-SDI = H
  • 3G-SDI = H
  • HD-SDI Dual Link = H
  • Dual rate = SD (1H 4L 1H 5L); HD (1H 1L)
  • Triple rate = SD (1H 4L 1H 5L); HD (1H 1L); 3G (H)
  • Multi rate (up to 12G) = SD (1H 4L 1H 5L); HD (1H 1L); 3G/6G/12G (H)
tx_dataout_valid_b 1 Output Data valid generated by the core for link B. The timing (H: High, L: Low) is identical to the tx_dataout_valid signal and is synchronous to tx_pclk clock domain.
Note: Applicable for HD-SDI dual link mode only.
tx_std_out 3 Output Indicates the transmitted video standard. This signal connects to tx_std in the transceiver only configuration.
Note: Applicable for 3G-SDI, dual-rate, and triple-rate transmitter protocol only configuration. Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile devices.
tx_vpid_overwrite 6 1 Input When a payload ID is embedded in the video stream, the core enables this signal to overwrite the existing payload ID. No effect when disabled.
Note: For the Transmitter Option – Insert Payload ID (SMPTE ST 352) and Enable active video data protocols = None only. The payload ID is always overwritten when Enable active video data protocols = AXIS-VVP Full.
tx_vpid_byte1 6 7 8S Input The core inserts payload ID byte 1.
tx_vpid_byte2 6 7 8S Input The core inserts payload ID byte 2.
tx_vpid_byte3 6 7 8S Input The core inserts payload ID byte 3.
tx_vpid_byte4 6 7 8S Input The core inserts payload ID byte 4.
tx_vpid_byte1_b 6 8S Input The core inserts payload ID byte 1 for link B. For 3G-SDI, HD-SDI dual link, triple-rate, and multi-rate (up to 12G) modes only.
tx_vpid_byte2_b 6 8 8S Input The core inserts payload ID byte 2 for link B. For 3G-SDI, HD-SDI dual link triple-rate, and multi-rate (up to 12G) modes only.
tx_vpid_byte3_b 6 8 8S Input The core inserts payload ID byte 3 for link B. For 3G-SDI, HD-SDI dual link, triple-rate, and multi-rate (up to 12G) modes only.
tx_vpid_byte4_b 6 8 8S Input The core inserts payload ID byte 4 for link B. For 3G-SDI, HD-SDI dual link, triple-rate, and multi-rate (up to 12G) modes only.
tx_line_f0 6 7 11S Input

Line number of field 0 (F0) of inserted payload ID. The line number must be valid and cannot be set to 0.
tx_line_f1 6 7 11S Input Line number of field 1 (F1) of inserted payload ID. The line number must be valid and cannot be set to 0.

Section Content
Image Mapping

4
  1. Not applicable for transceiver only configurations.
  2. Not applicable when Enable active video data protocols = AXIS-VVP Full. The CRC insertion is always enabled when Enable active video data protocols = AXIS-VVP Full.
5 Not applicable when Enable active video data protocols = AXIS-VVP Full.
6 Applicable only when you enable the Insert Payload ID (SMPTE ST 352) option.
7 For the Transmitter Option – Insert Payload ID (SMPTE ST 352) only and Enable active video data protocols = None.
8 For 3G-SDI, HD-SDI dual link, triple-rate, multi-rate (up to 12G), and Transmitter Option – Insert Payload ID (SMPTE ST 352) and Enable active video data protocols = None only.
Level Two Title